Re: xen/arm: uart interrupts handling

[Julien Grall <julien.grall@linaro.org>]

On 04/12/14 03:50, Vijay Kilari wrote:
> Hi Tim,

Hi Vijay,

> I see that on uart interrupt, ICR is written to clear the all
> interrupts except TX, RX and RX timeout. With this, cpu always finds
> TX/RX is active and never
> comes out of the loop.

FWIW, the PL011 serial code has been copied from the Linux drivers.

Linux interrupt handler also clear all interrupts except TX, RX, RX
timeout. So do you see the issue on Linux?

> 
> With the below changes, TX, RX & RTI are cleared before handling this
> interrupts.
> 
> Is my observation is correct?. If so I wonder how it is working on
> platforms that
> are using pl011. Without this for my cpu just keeps looping here.
> 
>   index fba0a55..d21bce3 100644
> --- a/xen/drivers/char/pl011.c
> +++ b/xen/drivers/char/pl011.c
> @@ -63,7 +63,7 @@ static void pl011_interrupt(int irq, void *data,
> struct cpu_user_regs *regs)
>      {
>          do
>          {
> -            pl011_write(uart, ICR, status & ~(TXI|RTI|RXI));
> +            pl011_write(uart, ICR, status & (TXI|RTI|RXI));


This changes looks wrong to me. We want to clear the bit in status we
don't handle. Otherwise the interrupt will be fired in loop.

If I'm not mistaken, TXI/RTI/RXI will be cleared when data is read or
write into the fifo. So we should not clear automatically.

Regards,

-- 
Julien Grall