From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46628) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XxzbG-0002PO-MW for qemu-devel@nongnu.org; Mon, 08 Dec 2014 09:47:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XxzbB-0002Bc-CO for qemu-devel@nongnu.org; Mon, 08 Dec 2014 09:47:46 -0500 Received: from [2001:41d0:8:2b42::1] (port=33795 helo=greensocs.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XxzbB-0002AY-6C for qemu-devel@nongnu.org; Mon, 08 Dec 2014 09:47:41 -0500 Message-ID: <5485BA0A.4010206@greensocs.com> Date: Mon, 08 Dec 2014 15:47:38 +0100 From: Frederic Konrad MIME-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] TCG multithread plan. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel , mttcg@listserver.greensocs.com Hi everybody, Here is the plan we will follow: We will be focusing - from the outset - on the end goal of multi-threaded= TCG in full system emulation mode. On the way, we expect this will =91fi= x=92 user mode. The plan is: * Create one cache per CPU as a first step. We can do more next and share= a cache. * Update tb_* to add a pointer to their cache. * Add atomic instruction support to the TGC (first on ARM). * Make tb_invalidate work between all cache. * Modify main-loop for multi-thread. * Memory access (eg: for device) are not thread safe that need to be fixe= d. Initial plan simply globally mutex memory accesses - this may be optim= ised later. * For now, irq handler for CPU seems ok but we need to check. We will discuss this during the call tomorrow. Thanks, Fred