From mboxrd@z Thu Jan  1 00:00:00 1970
From: Clemens Ladisch <clemens@ladisch.de>
Subject: Re: I2S frame configuration
Date: Mon, 08 Dec 2014 18:01:32 +0100
Message-ID: <5485D96C.3020900@ladisch.de>
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To: thomas chen <tchen61@gmail.com>, alsa-devel@alsa-project.org
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thomas chen wrote:
> I am working on a ALSA interface to a particular codec over I2S
>
> the audio stream format is a bit peculiar...
>
> there are 24 BCLK cycle between transition of FSYNC...   howver, there ar=
e only 16 bit that are valid
>
> bit 0: ignore
> bit 1-16:   valid pcm data (MSB....LSB)
> bit 17-23: ignore

This is the 'original' I=B2S format.  The format where the sample begins
with the 1st BCLK usually is called left-justified (and uses the
opposite FSYNC polarity).

Having ignored bits is common.  (Typically, there are 32 BCLK cycles per
sample.)

In ASoC, this would be SND_SOC_DAIFMT_I2S and SND_SOC_DAIFMT_LEFT_J.


Regards,
Clemens