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From: cyrille.pitchen@atmel.com (Cyrille Pitchen)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/1] net/macb: add TX multiqueue support for gem
Date: Fri, 12 Dec 2014 10:57:54 +0100	[thread overview]
Message-ID: <548ABC22.3080107@atmel.com> (raw)
In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6D1CA0BA7D@AcuExch.aculab.com>

Le 12/12/2014 10:59, David Laight a ?crit :
> From: Cyrille Pitchen [...
>>> It will probably add a lot of object code and, depending on how often
>>> the registers are accesses, might have performance impact.
>>>
>>> Having:
>>> #define GEM_ISR(n) (0x400 + (n) << 4)
>>> will save source code.
>>>
>>> 	David
>>>
>>>
>>>
>> So you suggest that we keep the unsigned int fields ISR, IMR, IER, IDR, TBQP in
>> the struct macb_queue and initialize them once for all in macb_probe() like
>> patch v2 does but only replace the GEM_ISR1 .. GEM_ISR7 defines by GEM_ISR(n)
>> in macb.h?
>>
>> This way there would be to test at run time and we can handle the special
>> register mapping of queue0.
>>
>> Is it what you meant?
> 
> In one word, yes.
> 
> 	David
> 
> 
> 
OK, so I'm working on v3

Thanks

Cyrille

WARNING: multiple messages have this Message-ID (diff)
From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
To: David Laight <David.Laight@ACULAB.COM>,
	"'Thomas Petazzoni'" <thomas.petazzoni@free-electrons.com>
Cc: "nicolas.ferre@atmel.com" <nicolas.ferre@atmel.com>,
	"davem@davemloft.net" <davem@davemloft.net>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"soren.brinkmann@xilinx.com" <soren.brinkmann@xilinx.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/1] net/macb: add TX multiqueue support for gem
Date: Fri, 12 Dec 2014 10:57:54 +0100	[thread overview]
Message-ID: <548ABC22.3080107@atmel.com> (raw)
In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6D1CA0BA7D@AcuExch.aculab.com>

Le 12/12/2014 10:59, David Laight a écrit :
> From: Cyrille Pitchen [...
>>> It will probably add a lot of object code and, depending on how often
>>> the registers are accesses, might have performance impact.
>>>
>>> Having:
>>> #define GEM_ISR(n) (0x400 + (n) << 4)
>>> will save source code.
>>>
>>> 	David
>>>
>>>
>>>
>> So you suggest that we keep the unsigned int fields ISR, IMR, IER, IDR, TBQP in
>> the struct macb_queue and initialize them once for all in macb_probe() like
>> patch v2 does but only replace the GEM_ISR1 .. GEM_ISR7 defines by GEM_ISR(n)
>> in macb.h?
>>
>> This way there would be to test at run time and we can handle the special
>> register mapping of queue0.
>>
>> Is it what you meant?
> 
> In one word, yes.
> 
> 	David
> 
> 
> 
OK, so I'm working on v3

Thanks

Cyrille

  reply	other threads:[~2014-12-12  9:57 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-12-11 10:16 [PATCH v2 0/1] net/macb: add TX multiqueue support for gem Cyrille Pitchen
2014-12-11 10:16 ` Cyrille Pitchen
2014-12-11 10:16 ` [PATCH v2 1/1] " Cyrille Pitchen
2014-12-11 10:16   ` Cyrille Pitchen
2014-12-11 19:31   ` Thomas Petazzoni
2014-12-11 19:31     ` Thomas Petazzoni
2014-12-12  8:24     ` Cyrille Pitchen
2014-12-12  8:24       ` Cyrille Pitchen
2014-12-12  9:45     ` David Laight
2014-12-12  9:45       ` David Laight
2014-12-12  8:59       ` Cyrille Pitchen
2014-12-12  8:59         ` Cyrille Pitchen
2014-12-12  9:59         ` David Laight
2014-12-12  9:59           ` David Laight
2014-12-12  9:57           ` Cyrille Pitchen [this message]
2014-12-12  9:57             ` Cyrille Pitchen
2014-12-12  9:52       ` Thomas Petazzoni
2014-12-12  9:52         ` Thomas Petazzoni

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