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Subject: Re: [Qemu-devel] [PATCH 2/8] target-tricore: Add instructions of RR
 opcode format, that have 0xb as the first opcode
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To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, qemu-devel@nongnu.org

On 12/12/2014 09:31 AM, Bastian Koppelmann wrote:
> +#define SSOV16(env, hw0, hw1) do {                  \
> +    int32_t max_pos = INT16_MAX;                    \
> +    int32_t max_neg = INT16_MIN;                    \
...
> +#define SUOV16(env, hw0, hw1) do {                  \
> +    int32_t max_pos = UINT16_MAX;                   \
> +    int32_t av0, av1;                               \

Similarly, make these functions.

Best if you have these functions return the combined word, i.e.

> +    return (ret_hw0 & 0xffff) | (ret_hw1 << 16);

so that you don't try to return the two separate inputs via reference.

> +/* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
> +static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
> +{
> +    TCGv temp = tcg_temp_new();
> +
> +    tcg_gen_setcond_tl(cond, temp, r1, r2);
> +    tcg_gen_movi_tl(ret, 0);
> +    tcg_gen_sub_tl(ret, ret, temp);

tcg_gen_neg_tl, at which point you don't need a temporary.



r~