From: Paolo Bonzini <pbonzini@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: mttcg@greensocs.com, Mark Burton <mark.burton@greensocs.com>,
Developers qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] Atomic Instructions - comments please
Date: Mon, 15 Dec 2014 14:28:07 +0100 [thread overview]
Message-ID: <548EE1E7.2090208@redhat.com> (raw)
In-Reply-To: <CAFEAcA_g=y6QnCHzoh7C6MTcTSp9b3Y+3AcP4r_1sh9DBMAQhQ@mail.gmail.com>
On 15/12/2014 14:23, Peter Maydell wrote:
> > What are the intended semantics for reads/writes from the outside world?
> > Should they cause the ll/sc pair to retry or not?
> Assuming that by "outside world" you mean "some other CPU in this
> cluster" [in ARM-speak, some other observer in the same shareability
> domain]: writes should. Reads should not.
No, I mean from DMA. Other CPU of course need to abort reads/writes.
The CPU that executes LL can invalidate the physical address on all
other CPUs' TLBs. Attempts to write to that address then would fill the
TLB entry with the new TLB_LL bit.
Paolo
next prev parent reply other threads:[~2014-12-15 13:28 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-15 12:56 [Qemu-devel] Atomic Instructions - comments please Mark Burton
2014-12-15 13:16 ` Paolo Bonzini
2014-12-15 13:23 ` Peter Maydell
2014-12-15 13:28 ` Paolo Bonzini [this message]
2014-12-15 13:36 ` Peter Maydell
2014-12-15 14:09 ` Peter Maydell
2014-12-15 13:28 ` Peter Maydell
2014-12-15 13:32 ` Paolo Bonzini
2014-12-15 13:37 ` Mark Burton
2014-12-15 13:39 ` Peter Maydell
2014-12-15 13:43 ` Mark Burton
2014-12-15 13:46 ` Paolo Bonzini
2014-12-15 13:35 ` Mark Burton
2014-12-15 18:15 ` Lluís Vilanova
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