From: Alexander Graf <agraf@suse.de>
To: Tom Musta <tommusta@gmail.com>,
qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields
Date: Thu, 18 Dec 2014 18:02:22 +0100 [thread overview]
Message-ID: <5493089E.1050109@suse.de> (raw)
In-Reply-To: <1418920477-11669-6-git-send-email-tommusta@gmail.com>
On 18.12.14 17:34, Tom Musta wrote:
> Define mnemonics for the various bit fields in the Transaction
> EXception And Summary Register (TEXASR).
This is missing an SoB line.
Alex
next prev parent reply other threads:[~2014-12-18 17:02 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 1/9] target-ppc: Introduce Instruction Type " Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 2/9] target-ppc: Introduce Feature Flag " Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 4/9] target-ppc: Power8 Supports Transactional Memory Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields Tom Musta
2014-12-18 17:02 ` Alexander Graf [this message]
2014-12-18 18:10 ` Tom Musta
2014-12-18 18:29 ` Alexander Graf
2014-12-18 18:41 ` Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 6/9] target-ppc: Introduce tbegin Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 7/9] target-ppc: Introduce TM Noops Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 8/9] target-ppc: Introduce tcheck Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops Tom Musta
2014-12-19 10:20 ` Fam Zheng
2014-12-20 21:22 ` Tom Musta
2014-12-18 22:52 ` [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Alexander Graf
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