From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ying.Liu@freescale.com (Liu Ying) Date: Fri, 19 Dec 2014 13:53:22 +0800 Subject: [PATCH RFC v2 08/14] drm: imx: Add MIPI DSI host controller driver In-Reply-To: <1418902740.4212.46.camel@pengutronix.de> References: <1418886696-11636-1-git-send-email-Ying.Liu@freescale.com> <1418886696-11636-9-git-send-email-Ying.Liu@freescale.com> <1418902740.4212.46.camel@pengutronix.de> Message-ID: <5493BD52.8070804@freescale.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 12/18/2014 07:39 PM, Philipp Zabel wrote: > Am Donnerstag, den 18.12.2014, 15:11 +0800 schrieb Liu Ying: >> This patch adds i.MX MIPI DSI host controller driver support. >> Currently, the driver supports the burst with sync pulses mode only. >> >> Signed-off-by: Liu Ying >> --- >> v1->v2: >> * Address almost all comments from Thierry Reding and Russell. >> * Update the DT documentation to remove the display-timings node in the panel node. >> * Update the DT documentation to state that the nodes which represent the possible >> DRM CRTCs the controller may connect with should be placed in the node "ports". >> * Remove the flag 'enabled' from the struct imx_mipi_dsi. >> * Move the format_to_bpp() function in v1 to the common DRM MIPI DSI driver. >> * Improve the way we wait for check status for DPHY and command packet transfer. >> * Improve the DPMS support for the encoder. >> * Split the functions of ->host_attach() and ->mode_valid() clearly as suggested by >> Thierry Reding. >> * Improve the logics in imx_mipi_dsi_dcs_long_write(). >> * Enable/disable the pllref_clk and pllref_gate_clk at the component binding/unbinding >> stages to help remove the flag 'enabled'. >> * Update the module license to be "GPL". >> * Other minor changes, such as coding style issues and macro naming issues. >> >> .../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++ >> drivers/gpu/drm/imx/Kconfig | 6 + >> drivers/gpu/drm/imx/Makefile | 1 + >> drivers/gpu/drm/imx/imx-mipi-dsi.c | 1056 ++++++++++++++++++++ >> 4 files changed, 1141 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt >> create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c >> >> diff --git a/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt >> new file mode 100644 >> index 0000000..892ed62 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt >> @@ -0,0 +1,78 @@ >> +Device-Tree bindings for MIPI DSI host controller >> + >> +MIPI DSI host controller >> +======================== >> + >> +The MIPI DSI host controller is a Synopsys DesignWare IP. >> +It is a digital core that implements all protocol functions defined >> +in the MIPI DSI specification, providing an interface between the >> +system and the MIPI DPHY, and allowing communication with a MIPI DSI >> +compliant display. >> + >> +Required properties: >> + - #address-cells: Should be <1>. >> + - #size-cells: Should be <0>. >> + - compatible: Should be "fsl,imx6q-mipi-dsi" for i.MX6q/sdl SoCs. > > If this is a Synopsys DesignWare IP core as the HDMI TX, I think the > compatible should reflect that. How about a second compatible > "snps,dw-mipi-dsi"? Ok, I'll add this second compatible string. > >> + - reg: Physical base address of the controller and length of memory >> + mapped region. >> + - interrupts: The controller's interrupt number to the CPU(s). >> + - gpr: Should be <&gpr>. >> + The phandle points to the iomuxc-gpr region containing the >> + multiplexer control register for the controller. >> + - clocks, clock-names: Phandles to the controller pllref, pllref_gate >> + and core_cfg clocks, as described in [1] and [2]. >> + >> +Required sub-nodes: >> + - ports: This node may contain up to four port nodes with endpoint >> + definitions as defined in [3], corresponding to the four inputs to >> + the controller multiplexer. >> + - A node to represent a DSI peripheral as described in [4]. >> + >> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt >> +[2] Documentation/devicetree/bindings/clock/imx6q-clock.txt >> +[3] Documentation/devicetree/bindings/media/video-interfaces.txt >> +[4] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt >> + >> +example: >> + gpr: iomuxc-gpr at 020e0000 { >> + /* ... */ >> + }; >> + >> + mipi_dsi: mipi at 021e0000 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "fsl,imx6q-mipi-dsi"; >> + reg = <0x021e0000 0x4000>; >> + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; >> + gpr = <&gpr>; >> + clocks = <&clks IMX6QDL_CLK_VIDEO_27M>, >> + <&clks IMX6QDL_CLK_HSI_TX>, >> + <&clks IMX6QDL_CLK_HSI_TX>; >> + clock-names = "pllref", "pllref_gate", "core_cfg"; > > Not sure about this. Are those names from the Synopsys documentation? No, I don't think it's from there. > > According to Table 41-1 in the i.MX6Q Reference Manual, this module has > 6 clock inputs: > - ac_clk_125m (from ahb_clk_root) > - pixel_clk (from axi_clk_root) > - cfg_clk and pll_refclk (from video_27m) > - ips_clk and ipg_clk_s (from ipg_clk_root) > The CCM chapter says that of these, "ac_clk_125m", "cfg_clk", ips_clk", > and "pll_refclk" are gated by a single bit called > "mipi_core_cfg_clk_enable", that is clk[CLK_HSI_TX]. > If that is correct, I see no reason for the "pllref_gate" clock. > I suppose two clocks "pllref" and "cfg" should suffice. Using the two clocks makes the code look like this, perhaps: clocks = <&clks IMX6QDL_CLK_VIDEO_27M>, <&clks IMX6QDL_CLK_HSI_TX>; clock-names = "pllref", "core_cfg"; Then, it seems that I have no way to disable the pllref clock if using the clock tree after applying this patch set? Or, perhaps, this one? clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_HSI_TX>; clock-names = "pllref", "core_cfg"; This only uses the gate clock hsi_tx. The current clock tree states that it comes from: pll3_120m -> | -> hsi_tx_sel -> hsi_tx_podf -> hsi_tx pll2_pfd2_396m -> So, I can not get the correct pllref clock frequency with this tree. The pllref clock should be derived from the video_27m clock. The way I decided to use the three clocks is: 1) PLL related * pllref clock only cares about the pll reference rate(the frequency). And, the frequency does matter as it has an impact on the lane clock frequency. * pllref_gate is a gate clock and it only cares about the gate. 2) register configuration related * core_cfg is a gate clock and it only cares about the gate. Usually, the register configuration clock frequency is not so important and the gate is what we really need. I am currently not strong on the way I used. I am open to any better solution. > > Maybe HSI_TX should be split up into multiple shared gate clocks that > all set the mipi_core_cfg clock bits (see below). Yes, maybe. If that's the case, do we need to add two gate clocks in the DT node to represent cfg_gate and pllref_gate respectively? > >> diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig >> index 82fb758..03f04fb 100644 >> --- a/drivers/gpu/drm/imx/Kconfig >> +++ b/drivers/gpu/drm/imx/Kconfig >> @@ -51,3 +51,9 @@ config DRM_IMX_HDMI >> depends on DRM_IMX >> help >> Choose this if you want to use HDMI on i.MX6. >> + >> +config DRM_IMX_MIPI_DSI >> + tristate "Freescale i.MX DRM MIPI DSI" >> + depends on DRM_IMX && MFD_SYSCON >> + help >> + Choose this if you want to use MIPI DSI on i.MX6. >> diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile >> index 582c438..4571d52 100644 >> --- a/drivers/gpu/drm/imx/Makefile >> +++ b/drivers/gpu/drm/imx/Makefile >> @@ -10,3 +10,4 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o >> imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o >> obj-$(CONFIG_DRM_IMX_IPUV3) += imx-ipuv3-crtc.o >> obj-$(CONFIG_DRM_IMX_HDMI) += imx-hdmi.o >> +obj-$(CONFIG_DRM_IMX_MIPI_DSI) += imx-mipi-dsi.o >> diff --git a/drivers/gpu/drm/imx/imx-mipi-dsi.c b/drivers/gpu/drm/imx/imx-mipi-dsi.c >> new file mode 100644 >> index 0000000..1cb4328 >> --- /dev/null >> +++ b/drivers/gpu/drm/imx/imx-mipi-dsi.c > [...] >> +static int imx_mipi_dsi_bind(struct device *dev, struct device *master, void *data) >> +{ >> + struct platform_device *pdev = to_platform_device(dev); >> + struct drm_device *drm = data; >> + struct device_node *np = dev->of_node; >> + struct imx_mipi_dsi *dsi; >> + struct resource *res; >> + u32 val; >> + int ret; >> + >> + dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); >> + if (!dsi) >> + return -ENOMEM; >> + >> + dsi->dev = dev; >> + dsi->dsi_host.ops = &imx_mipi_dsi_host_ops; >> + dsi->dsi_host.dev = dev; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + dsi->base = devm_ioremap_resource(dev, res); >> + if (IS_ERR(dsi->base)) >> + return PTR_ERR(dsi->base); >> + >> + dsi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); >> + if (IS_ERR(dsi->regmap)) >> + return PTR_ERR(dsi->regmap); >> + >> + dsi->pllref_clk = devm_clk_get(dev, "pllref"); >> + if (IS_ERR(dsi->pllref_clk)) { >> + ret = PTR_ERR(dsi->pllref_clk); >> + dev_err(dev, "Unable to get pll reference clock: %d\n", ret); >> + return ret; >> + } >> + clk_prepare_enable(dsi->pllref_clk); >> + >> + dsi->pllref_gate_clk = devm_clk_get(dev, "pllref_gate"); >> + if (IS_ERR(dsi->pllref_gate_clk)) { >> + ret = PTR_ERR(dsi->pllref_gate_clk); >> + dev_err(dev, "Unable to get pll reference gate clock: %d\n", ret); >> + return ret; >> + } >> + clk_prepare_enable(dsi->pllref_gate_clk); > > As said above, I don't think this clock is needed, or is it? Perhaps, we need it. > > If enabling pllref_clk doesn't actually enable the 27m clock input to > the mipi dsi core because it is still gated by hsi_tx, maybe the clock > tree should be fixed and hsi_tx turned into multiple > imx_clk_gate2_shared clocks. According to the CCM chapter, the video_27m clock is gated by the hsi_tx clock. You mentioned this above, as well. > >> + >> + dsi->cfg_clk = devm_clk_get(dev, "core_cfg"); >> + if (IS_ERR(dsi->cfg_clk)) { >> + ret = PTR_ERR(dsi->cfg_clk); >> + dev_err(dev, "Unable to get configuration clock: %d\n", ret); > > And leave pllref enabled? As I mentioned in the v1-> v2 change log, I enable/disable the pllref_clk and pllref_gate_clk at the component binding/unbinding stages to help remove the flag 'enabled' introduced in v1. I referred to the i.MX HDMI driver which enables/disables the isfr clock and the iahb clock at the component binding/unbinding stages. I may try to handle the clock enablement/disablement more decently and avoid using the flag 'enable'. > >> + return ret; >> + } >> + >> + clk_prepare_enable(dsi->cfg_clk); >> + val = dsi_read(dsi, DSI_VERSION); >> + clk_disable_unprepare(dsi->cfg_clk); >> + >> + dev_info(dev, "version number is 0x%08x\n", val); >> + >> + ret = imx_mipi_dsi_register(drm, dsi); >> + if (ret) > > Same here. You meant that the pllref_gate clock is left enabled above, right? Regards, Liu Ying > >> + return ret; >> + >> + dev_set_drvdata(dev, dsi); >> + >> + return mipi_dsi_host_register(&dsi->dsi_host); >> +} > [...] > > regards > Philipp > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Liu Ying Subject: Re: [PATCH RFC v2 08/14] drm: imx: Add MIPI DSI host controller driver Date: Fri, 19 Dec 2014 13:53:22 +0800 Message-ID: <5493BD52.8070804@freescale.com> References: <1418886696-11636-1-git-send-email-Ying.Liu@freescale.com> <1418886696-11636-9-git-send-email-Ying.Liu@freescale.com> <1418902740.4212.46.camel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1418902740.4212.46.camel@pengutronix.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Philipp Zabel Cc: devicetree@vger.kernel.org, linux@arm.linux.org.uk, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@pengutronix.de, mturquette@linaro.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org T24gMTIvMTgvMjAxNCAwNzozOSBQTSwgUGhpbGlwcCBaYWJlbCB3cm90ZToKPiBBbSBEb25uZXJz dGFnLCBkZW4gMTguMTIuMjAxNCwgMTU6MTEgKzA4MDAgc2NocmllYiBMaXUgWWluZzoKPj4gVGhp cyBwYXRjaCBhZGRzIGkuTVggTUlQSSBEU0kgaG9zdCBjb250cm9sbGVyIGRyaXZlciBzdXBwb3J0 Lgo+PiBDdXJyZW50bHksIHRoZSBkcml2ZXIgc3VwcG9ydHMgdGhlIGJ1cnN0IHdpdGggc3luYyBw dWxzZXMgbW9kZSBvbmx5Lgo+Pgo+PiBTaWduZWQtb2ZmLWJ5OiBMaXUgWWluZyA8WWluZy5MaXVA ZnJlZXNjYWxlLmNvbT4KPj4gLS0tCj4+IHYxLT52MjoKPj4gICAqIEFkZHJlc3MgYWxtb3N0IGFs bCBjb21tZW50cyBmcm9tIFRoaWVycnkgUmVkaW5nIGFuZCBSdXNzZWxsLgo+PiAgICogVXBkYXRl IHRoZSBEVCBkb2N1bWVudGF0aW9uIHRvIHJlbW92ZSB0aGUgZGlzcGxheS10aW1pbmdzIG5vZGUg aW4gdGhlIHBhbmVsIG5vZGUuCj4+ICAgKiBVcGRhdGUgdGhlIERUIGRvY3VtZW50YXRpb24gdG8g c3RhdGUgdGhhdCB0aGUgbm9kZXMgd2hpY2ggcmVwcmVzZW50IHRoZSBwb3NzaWJsZQo+PiAgICAg RFJNIENSVENzIHRoZSBjb250cm9sbGVyIG1heSBjb25uZWN0IHdpdGggc2hvdWxkIGJlIHBsYWNl ZCBpbiB0aGUgbm9kZSAicG9ydHMiLgo+PiAgICogUmVtb3ZlIHRoZSBmbGFnICdlbmFibGVkJyBm cm9tIHRoZSBzdHJ1Y3QgaW14X21pcGlfZHNpLgo+PiAgICogTW92ZSB0aGUgZm9ybWF0X3RvX2Jw cCgpIGZ1bmN0aW9uIGluIHYxIHRvIHRoZSBjb21tb24gRFJNIE1JUEkgRFNJIGRyaXZlci4KPj4g ICAqIEltcHJvdmUgdGhlIHdheSB3ZSB3YWl0IGZvciBjaGVjayBzdGF0dXMgZm9yIERQSFkgYW5k IGNvbW1hbmQgcGFja2V0IHRyYW5zZmVyLgo+PiAgICogSW1wcm92ZSB0aGUgRFBNUyBzdXBwb3J0 IGZvciB0aGUgZW5jb2Rlci4KPj4gICAqIFNwbGl0IHRoZSBmdW5jdGlvbnMgb2YgLT5ob3N0X2F0 dGFjaCgpIGFuZCAtPm1vZGVfdmFsaWQoKSBjbGVhcmx5IGFzIHN1Z2dlc3RlZCBieQo+PiAgICAg VGhpZXJyeSBSZWRpbmcuCj4+ICAgKiBJbXByb3ZlIHRoZSBsb2dpY3MgaW4gaW14X21pcGlfZHNp X2Rjc19sb25nX3dyaXRlKCkuCj4+ICAgKiBFbmFibGUvZGlzYWJsZSB0aGUgcGxscmVmX2NsayBh bmQgcGxscmVmX2dhdGVfY2xrIGF0IHRoZSBjb21wb25lbnQgYmluZGluZy91bmJpbmRpbmcKPj4g ICAgIHN0YWdlcyB0byBoZWxwIHJlbW92ZSB0aGUgZmxhZyAnZW5hYmxlZCcuCj4+ICAgKiBVcGRh dGUgdGhlIG1vZHVsZSBsaWNlbnNlIHRvIGJlICJHUEwiLgo+PiAgICogT3RoZXIgbWlub3IgY2hh bmdlcywgc3VjaCBhcyBjb2Rpbmcgc3R5bGUgaXNzdWVzIGFuZCBtYWNybyBuYW1pbmcgaXNzdWVz Lgo+Pgo+PiAgIC4uLi9kZXZpY2V0cmVlL2JpbmRpbmdzL2RybS9pbXgvbWlwaV9kc2kudHh0ICAg ICAgIHwgICA3OCArKwo+PiAgIGRyaXZlcnMvZ3B1L2RybS9pbXgvS2NvbmZpZyAgICAgICAgICAg ICAgICAgICAgICAgIHwgICAgNiArCj4+ICAgZHJpdmVycy9ncHUvZHJtL2lteC9NYWtlZmlsZSAg ICAgICAgICAgICAgICAgICAgICAgfCAgICAxICsKPj4gICBkcml2ZXJzL2dwdS9kcm0vaW14L2lt eC1taXBpLWRzaS5jICAgICAgICAgICAgICAgICB8IDEwNTYgKysrKysrKysrKysrKysrKysrKysK Pj4gICA0IGZpbGVzIGNoYW5nZWQsIDExNDEgaW5zZXJ0aW9ucygrKQo+PiAgIGNyZWF0ZSBtb2Rl IDEwMDY0NCBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZHJtL2lteC9taXBpX2Rz aS50eHQKPj4gICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL2lteC9pbXgtbWlw aS1kc2kuYwo+Pgo+PiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRp bmdzL2RybS9pbXgvbWlwaV9kc2kudHh0IGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRp bmdzL2RybS9pbXgvbWlwaV9kc2kudHh0Cj4+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4+IGluZGV4 IDAwMDAwMDAuLjg5MmVkNjIKPj4gLS0tIC9kZXYvbnVsbAo+PiArKysgYi9Eb2N1bWVudGF0aW9u L2RldmljZXRyZWUvYmluZGluZ3MvZHJtL2lteC9taXBpX2RzaS50eHQKPj4gQEAgLTAsMCArMSw3 OCBAQAo+PiArRGV2aWNlLVRyZWUgYmluZGluZ3MgZm9yIE1JUEkgRFNJIGhvc3QgY29udHJvbGxl cgo+PiArCj4+ICtNSVBJIERTSSBob3N0IGNvbnRyb2xsZXIKPj4gKz09PT09PT09PT09PT09PT09 PT09PT09PQo+PiArCj4+ICtUaGUgTUlQSSBEU0kgaG9zdCBjb250cm9sbGVyIGlzIGEgU3lub3Bz eXMgRGVzaWduV2FyZSBJUC4KPj4gK0l0IGlzIGEgZGlnaXRhbCBjb3JlIHRoYXQgaW1wbGVtZW50 cyBhbGwgcHJvdG9jb2wgZnVuY3Rpb25zIGRlZmluZWQKPj4gK2luIHRoZSBNSVBJIERTSSBzcGVj aWZpY2F0aW9uLCBwcm92aWRpbmcgYW4gaW50ZXJmYWNlIGJldHdlZW4gdGhlCj4+ICtzeXN0ZW0g YW5kIHRoZSBNSVBJIERQSFksIGFuZCBhbGxvd2luZyBjb21tdW5pY2F0aW9uIHdpdGggYSBNSVBJ IERTSQo+PiArY29tcGxpYW50IGRpc3BsYXkuCj4+ICsKPj4gK1JlcXVpcmVkIHByb3BlcnRpZXM6 Cj4+ICsgLSAjYWRkcmVzcy1jZWxsczogU2hvdWxkIGJlIDwxPi4KPj4gKyAtICNzaXplLWNlbGxz OiBTaG91bGQgYmUgPDA+Lgo+PiArIC0gY29tcGF0aWJsZTogU2hvdWxkIGJlICJmc2wsaW14NnEt bWlwaS1kc2kiIGZvciBpLk1YNnEvc2RsIFNvQ3MuCj4KPiBJZiB0aGlzIGlzIGEgU3lub3BzeXMg RGVzaWduV2FyZSBJUCBjb3JlIGFzIHRoZSBIRE1JIFRYLCBJIHRoaW5rIHRoZQo+IGNvbXBhdGli bGUgc2hvdWxkIHJlZmxlY3QgdGhhdC4gSG93IGFib3V0IGEgc2Vjb25kIGNvbXBhdGlibGUKPiAi c25wcyxkdy1taXBpLWRzaSI/CgpPaywgSSdsbCBhZGQgdGhpcyBzZWNvbmQgY29tcGF0aWJsZSBz dHJpbmcuCgo+Cj4+ICsgLSByZWc6IFBoeXNpY2FsIGJhc2UgYWRkcmVzcyBvZiB0aGUgY29udHJv bGxlciBhbmQgbGVuZ3RoIG9mIG1lbW9yeQo+PiArICAgICAgICAgbWFwcGVkIHJlZ2lvbi4KPj4g KyAtIGludGVycnVwdHM6IFRoZSBjb250cm9sbGVyJ3MgaW50ZXJydXB0IG51bWJlciB0byB0aGUg Q1BVKHMpLgo+PiArIC0gZ3ByOiBTaG91bGQgYmUgPCZncHI+Lgo+PiArICAgICAgICAgVGhlIHBo YW5kbGUgcG9pbnRzIHRvIHRoZSBpb211eGMtZ3ByIHJlZ2lvbiBjb250YWluaW5nIHRoZQo+PiAr ICAgICAgICAgbXVsdGlwbGV4ZXIgY29udHJvbCByZWdpc3RlciBmb3IgdGhlIGNvbnRyb2xsZXIu Cj4+ICsgLSBjbG9ja3MsIGNsb2NrLW5hbWVzOiBQaGFuZGxlcyB0byB0aGUgY29udHJvbGxlciBw bGxyZWYsIHBsbHJlZl9nYXRlCj4+ICsgICAgICAgICAgIGFuZCBjb3JlX2NmZyBjbG9ja3MsIGFz IGRlc2NyaWJlZCBpbiBbMV0gYW5kIFsyXS4KPj4gKwo+PiArUmVxdWlyZWQgc3ViLW5vZGVzOgo+ PiArIC0gcG9ydHM6IFRoaXMgbm9kZSBtYXkgY29udGFpbiB1cCB0byBmb3VyIHBvcnQgbm9kZXMg d2l0aCBlbmRwb2ludAo+PiArICAgZGVmaW5pdGlvbnMgYXMgZGVmaW5lZCBpbiBbM10sIGNvcnJl c3BvbmRpbmcgdG8gdGhlIGZvdXIgaW5wdXRzIHRvCj4+ICsgICB0aGUgY29udHJvbGxlciBtdWx0 aXBsZXhlci4KPj4gKyAtIEEgbm9kZSB0byByZXByZXNlbnQgYSBEU0kgcGVyaXBoZXJhbCBhcyBk ZXNjcmliZWQgaW4gWzRdLgo+PiArCj4+ICtbMV0gRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2Jp bmRpbmdzL2Nsb2NrL2Nsb2NrLWJpbmRpbmdzLnR4dAo+PiArWzJdIERvY3VtZW50YXRpb24vZGV2 aWNldHJlZS9iaW5kaW5ncy9jbG9jay9pbXg2cS1jbG9jay50eHQKPj4gK1szXSBEb2N1bWVudGF0 aW9uL2RldmljZXRyZWUvYmluZGluZ3MvbWVkaWEvdmlkZW8taW50ZXJmYWNlcy50eHQKPj4gK1s0 XSBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvbWlwaS9kc2kvbWlwaS1kc2ktYnVz LnR4dAo+PiArCj4+ICtleGFtcGxlOgo+PiArCWdwcjogaW9tdXhjLWdwckAwMjBlMDAwMCB7Cj4+ ICsJCS8qIC4uLiAqLwo+PiArCX07Cj4+ICsKPj4gKwltaXBpX2RzaTogbWlwaUAwMjFlMDAwMCB7 Cj4+ICsJCSNhZGRyZXNzLWNlbGxzID0gPDE+Owo+PiArCQkjc2l6ZS1jZWxscyA9IDwwPjsKPj4g KwkJY29tcGF0aWJsZSA9ICJmc2wsaW14NnEtbWlwaS1kc2kiOwo+PiArCQlyZWcgPSA8MHgwMjFl MDAwMCAweDQwMDA+Owo+PiArCQlpbnRlcnJ1cHRzID0gPDAgMTAyIElSUV9UWVBFX0xFVkVMX0hJ R0g+Owo+PiArCQlncHIgPSA8Jmdwcj47Cj4+ICsJCWNsb2NrcyA9IDwmY2xrcyBJTVg2UURMX0NM S19WSURFT18yN00+LAo+PiArCQkJIDwmY2xrcyBJTVg2UURMX0NMS19IU0lfVFg+LAo+PiArCQkJ IDwmY2xrcyBJTVg2UURMX0NMS19IU0lfVFg+Owo+PiArCQljbG9jay1uYW1lcyA9ICJwbGxyZWYi LCAicGxscmVmX2dhdGUiLCAiY29yZV9jZmciOwo+Cj4gTm90IHN1cmUgYWJvdXQgdGhpcy4gQXJl IHRob3NlIG5hbWVzIGZyb20gdGhlIFN5bm9wc3lzIGRvY3VtZW50YXRpb24/CgpObywgSSBkb24n dCB0aGluayBpdCdzIGZyb20gdGhlcmUuCgo+Cj4gQWNjb3JkaW5nIHRvIFRhYmxlIDQxLTEgaW4g dGhlIGkuTVg2USBSZWZlcmVuY2UgTWFudWFsLCB0aGlzIG1vZHVsZSBoYXMKPiA2IGNsb2NrIGlu cHV0czoKPiAgIC0gYWNfY2xrXzEyNW0gKGZyb20gYWhiX2Nsa19yb290KQo+ICAgLSBwaXhlbF9j bGsgKGZyb20gYXhpX2Nsa19yb290KQo+ICAgLSBjZmdfY2xrIGFuZCBwbGxfcmVmY2xrIChmcm9t IHZpZGVvXzI3bSkKPiAgIC0gaXBzX2NsayBhbmQgaXBnX2Nsa19zIChmcm9tIGlwZ19jbGtfcm9v dCkKPiBUaGUgQ0NNIGNoYXB0ZXIgc2F5cyB0aGF0IG9mIHRoZXNlLCAiYWNfY2xrXzEyNW0iLCAi Y2ZnX2NsayIsIGlwc19jbGsiLAo+IGFuZCAicGxsX3JlZmNsayIgYXJlIGdhdGVkIGJ5IGEgc2lu Z2xlIGJpdCBjYWxsZWQKPiAibWlwaV9jb3JlX2NmZ19jbGtfZW5hYmxlIiwgdGhhdCBpcyBjbGtb Q0xLX0hTSV9UWF0uCj4gSWYgdGhhdCBpcyBjb3JyZWN0LCBJIHNlZSBubyByZWFzb24gZm9yIHRo ZSAicGxscmVmX2dhdGUiIGNsb2NrLgo+IEkgc3VwcG9zZSB0d28gY2xvY2tzICJwbGxyZWYiIGFu ZCAiY2ZnIiBzaG91bGQgc3VmZmljZS4KClVzaW5nIHRoZSB0d28gY2xvY2tzIG1ha2VzIHRoZSBj b2RlIGxvb2sgbGlrZSB0aGlzLCBwZXJoYXBzOgoKICAgICAgIGNsb2NrcyA9IDwmY2xrcyBJTVg2 UURMX0NMS19WSURFT18yN00+LAogICAgICAgICAgICAgICAgPCZjbGtzIElNWDZRRExfQ0xLX0hT SV9UWD47CiAgICAgICBjbG9jay1uYW1lcyA9ICJwbGxyZWYiLCAiY29yZV9jZmciOwoKVGhlbiwg aXQgc2VlbXMgdGhhdCBJIGhhdmUgbm8gd2F5IHRvIGRpc2FibGUgdGhlIHBsbHJlZiBjbG9jayBp Zgp1c2luZyB0aGUgY2xvY2sgdHJlZSBhZnRlciBhcHBseWluZyB0aGlzIHBhdGNoIHNldD8KCgpP ciwgcGVyaGFwcywgdGhpcyBvbmU/CgogICAgICAgY2xvY2tzID0gPCZjbGtzIElNWDZRRExfQ0xL X0hTSV9UWD4sCiAgICAgICAgICAgICAgICA8JmNsa3MgSU1YNlFETF9DTEtfSFNJX1RYPjsKICAg ICAgIGNsb2NrLW5hbWVzID0gInBsbHJlZiIsICJjb3JlX2NmZyI7CgpUaGlzIG9ubHkgdXNlcyB0 aGUgZ2F0ZSBjbG9jayBoc2lfdHguICBUaGUgY3VycmVudCBjbG9jayB0cmVlIHN0YXRlcwp0aGF0 IGl0IGNvbWVzIGZyb206CgogICAgICBwbGwzXzEyMG0gLT4KICAgICAgICAgICAgICAgICAgfCAt PiBoc2lfdHhfc2VsIC0+IGhzaV90eF9wb2RmIC0+IGhzaV90eApwbGwyX3BmZDJfMzk2bSAtPgoK U28sIEkgY2FuIG5vdCBnZXQgdGhlIGNvcnJlY3QgcGxscmVmIGNsb2NrIGZyZXF1ZW5jeSB3aXRo IHRoaXMgdHJlZS4KVGhlIHBsbHJlZiBjbG9jayBzaG91bGQgYmUgZGVyaXZlZCBmcm9tIHRoZSB2 aWRlb18yN20gY2xvY2suCgoKVGhlIHdheSBJIGRlY2lkZWQgdG8gdXNlIHRoZSB0aHJlZSBjbG9j a3MgaXM6CjEpIFBMTCByZWxhdGVkCiogcGxscmVmIGNsb2NrIG9ubHkgY2FyZXMgYWJvdXQgdGhl IHBsbCByZWZlcmVuY2UgcmF0ZSh0aGUgZnJlcXVlbmN5KS4KICAgQW5kLCB0aGUgZnJlcXVlbmN5 IGRvZXMgbWF0dGVyIGFzIGl0IGhhcyBhbiBpbXBhY3Qgb24gdGhlIGxhbmUgY2xvY2sKICAgZnJl cXVlbmN5LgoqIHBsbHJlZl9nYXRlIGlzIGEgZ2F0ZSBjbG9jayBhbmQgaXQgb25seSBjYXJlcyBh Ym91dCB0aGUgZ2F0ZS4KCjIpIHJlZ2lzdGVyIGNvbmZpZ3VyYXRpb24gcmVsYXRlZAoqIGNvcmVf Y2ZnIGlzIGEgZ2F0ZSBjbG9jayBhbmQgaXQgb25seSBjYXJlcyBhYm91dCB0aGUgZ2F0ZS4KVXN1 YWxseSwgdGhlIHJlZ2lzdGVyIGNvbmZpZ3VyYXRpb24gY2xvY2sgZnJlcXVlbmN5IGlzIG5vdCBz byBpbXBvcnRhbnQKYW5kIHRoZSBnYXRlIGlzIHdoYXQgd2UgcmVhbGx5IG5lZWQuCgpJIGFtIGN1 cnJlbnRseSBub3Qgc3Ryb25nIG9uIHRoZSB3YXkgSSB1c2VkLiAgSSBhbSBvcGVuIHRvIGFueSBi ZXR0ZXIKc29sdXRpb24uCgo+Cj4gTWF5YmUgSFNJX1RYIHNob3VsZCBiZSBzcGxpdCB1cCBpbnRv IG11bHRpcGxlIHNoYXJlZCBnYXRlIGNsb2NrcyB0aGF0Cj4gYWxsIHNldCB0aGUgbWlwaV9jb3Jl X2NmZyBjbG9jayBiaXRzIChzZWUgYmVsb3cpLgoKWWVzLCBtYXliZS4KSWYgdGhhdCdzIHRoZSBj YXNlLCBkbyB3ZSBuZWVkIHRvIGFkZCB0d28gZ2F0ZSBjbG9ja3MgaW4gdGhlIERUIG5vZGUgdG8K cmVwcmVzZW50IGNmZ19nYXRlIGFuZCBwbGxyZWZfZ2F0ZSByZXNwZWN0aXZlbHk/Cgo+Cj4+IGRp ZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaW14L0tjb25maWcgYi9kcml2ZXJzL2dwdS9kcm0v aW14L0tjb25maWcKPj4gaW5kZXggODJmYjc1OC4uMDNmMDRmYiAxMDA2NDQKPj4gLS0tIGEvZHJp dmVycy9ncHUvZHJtL2lteC9LY29uZmlnCj4+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pbXgvS2Nv bmZpZwo+PiBAQCAtNTEsMyArNTEsOSBAQCBjb25maWcgRFJNX0lNWF9IRE1JCj4+ICAgCWRlcGVu ZHMgb24gRFJNX0lNWAo+PiAgIAloZWxwCj4+ICAgCSAgQ2hvb3NlIHRoaXMgaWYgeW91IHdhbnQg dG8gdXNlIEhETUkgb24gaS5NWDYuCj4+ICsKPj4gK2NvbmZpZyBEUk1fSU1YX01JUElfRFNJCj4+ ICsJdHJpc3RhdGUgIkZyZWVzY2FsZSBpLk1YIERSTSBNSVBJIERTSSIKPj4gKwlkZXBlbmRzIG9u IERSTV9JTVggJiYgTUZEX1NZU0NPTgo+PiArCWhlbHAKPj4gKwkgIENob29zZSB0aGlzIGlmIHlv dSB3YW50IHRvIHVzZSBNSVBJIERTSSBvbiBpLk1YNi4KPj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMv Z3B1L2RybS9pbXgvTWFrZWZpbGUgYi9kcml2ZXJzL2dwdS9kcm0vaW14L01ha2VmaWxlCj4+IGlu ZGV4IDU4MmM0MzguLjQ1NzFkNTIgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pbXgv TWFrZWZpbGUKPj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2lteC9NYWtlZmlsZQo+PiBAQCAtMTAs MyArMTAsNCBAQCBvYmotJChDT05GSUdfRFJNX0lNWF9MREIpICs9IGlteC1sZGIubwo+PiAgIGlt eC1pcHV2My1jcnRjLW9ianMgIDo9IGlwdXYzLWNydGMubyBpcHV2My1wbGFuZS5vCj4+ICAgb2Jq LSQoQ09ORklHX0RSTV9JTVhfSVBVVjMpCSs9IGlteC1pcHV2My1jcnRjLm8KPj4gICBvYmotJChD T05GSUdfRFJNX0lNWF9IRE1JKSArPSBpbXgtaGRtaS5vCj4+ICtvYmotJChDT05GSUdfRFJNX0lN WF9NSVBJX0RTSSkgKz0gaW14LW1pcGktZHNpLm8KPj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1 L2RybS9pbXgvaW14LW1pcGktZHNpLmMgYi9kcml2ZXJzL2dwdS9kcm0vaW14L2lteC1taXBpLWRz aS5jCj4+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4+IGluZGV4IDAwMDAwMDAuLjFjYjQzMjgKPj4g LS0tIC9kZXYvbnVsbAo+PiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaW14L2lteC1taXBpLWRzaS5j Cj4gWy4uLl0KPj4gK3N0YXRpYyBpbnQgaW14X21pcGlfZHNpX2JpbmQoc3RydWN0IGRldmljZSAq ZGV2LCBzdHJ1Y3QgZGV2aWNlICptYXN0ZXIsIHZvaWQgKmRhdGEpCj4+ICt7Cj4+ICsJc3RydWN0 IHBsYXRmb3JtX2RldmljZSAqcGRldiA9IHRvX3BsYXRmb3JtX2RldmljZShkZXYpOwo+PiArCXN0 cnVjdCBkcm1fZGV2aWNlICpkcm0gPSBkYXRhOwo+PiArCXN0cnVjdCBkZXZpY2Vfbm9kZSAqbnAg PSBkZXYtPm9mX25vZGU7Cj4+ICsJc3RydWN0IGlteF9taXBpX2RzaSAqZHNpOwo+PiArCXN0cnVj dCByZXNvdXJjZSAqcmVzOwo+PiArCXUzMiB2YWw7Cj4+ICsJaW50IHJldDsKPj4gKwo+PiArCWRz aSA9IGRldm1fa3phbGxvYyhkZXYsIHNpemVvZigqZHNpKSwgR0ZQX0tFUk5FTCk7Cj4+ICsJaWYg KCFkc2kpCj4+ICsJCXJldHVybiAtRU5PTUVNOwo+PiArCj4+ICsJZHNpLT5kZXYgPSBkZXY7Cj4+ ICsJZHNpLT5kc2lfaG9zdC5vcHMgPSAmaW14X21pcGlfZHNpX2hvc3Rfb3BzOwo+PiArCWRzaS0+ ZHNpX2hvc3QuZGV2ID0gZGV2Owo+PiArCj4+ICsJcmVzID0gcGxhdGZvcm1fZ2V0X3Jlc291cmNl KHBkZXYsIElPUkVTT1VSQ0VfTUVNLCAwKTsKPj4gKwlkc2ktPmJhc2UgPSBkZXZtX2lvcmVtYXBf cmVzb3VyY2UoZGV2LCByZXMpOwo+PiArCWlmIChJU19FUlIoZHNpLT5iYXNlKSkKPj4gKwkJcmV0 dXJuIFBUUl9FUlIoZHNpLT5iYXNlKTsKPj4gKwo+PiArCWRzaS0+cmVnbWFwID0gc3lzY29uX3Jl Z21hcF9sb29rdXBfYnlfcGhhbmRsZShucCwgImdwciIpOwo+PiArCWlmIChJU19FUlIoZHNpLT5y ZWdtYXApKQo+PiArCQlyZXR1cm4gUFRSX0VSUihkc2ktPnJlZ21hcCk7Cj4+ICsKPj4gKwlkc2kt PnBsbHJlZl9jbGsgPSBkZXZtX2Nsa19nZXQoZGV2LCAicGxscmVmIik7Cj4+ICsJaWYgKElTX0VS Uihkc2ktPnBsbHJlZl9jbGspKSB7Cj4+ICsJCXJldCA9IFBUUl9FUlIoZHNpLT5wbGxyZWZfY2xr KTsKPj4gKwkJZGV2X2VycihkZXYsICJVbmFibGUgdG8gZ2V0IHBsbCByZWZlcmVuY2UgY2xvY2s6 ICVkXG4iLCByZXQpOwo+PiArCQlyZXR1cm4gcmV0Owo+PiArCX0KPj4gKwljbGtfcHJlcGFyZV9l bmFibGUoZHNpLT5wbGxyZWZfY2xrKTsKPj4gKwo+PiArCWRzaS0+cGxscmVmX2dhdGVfY2xrID0g ZGV2bV9jbGtfZ2V0KGRldiwgInBsbHJlZl9nYXRlIik7Cj4+ICsJaWYgKElTX0VSUihkc2ktPnBs bHJlZl9nYXRlX2NsaykpIHsKPj4gKwkJcmV0ID0gUFRSX0VSUihkc2ktPnBsbHJlZl9nYXRlX2Ns ayk7Cj4+ICsJCWRldl9lcnIoZGV2LCAiVW5hYmxlIHRvIGdldCBwbGwgcmVmZXJlbmNlIGdhdGUg Y2xvY2s6ICVkXG4iLCByZXQpOwo+PiArCQlyZXR1cm4gcmV0Owo+PiArCX0KPj4gKwljbGtfcHJl cGFyZV9lbmFibGUoZHNpLT5wbGxyZWZfZ2F0ZV9jbGspOwo+Cj4gQXMgc2FpZCBhYm92ZSwgSSBk b24ndCB0aGluayB0aGlzIGNsb2NrIGlzIG5lZWRlZCwgb3IgaXMgaXQ/CgpQZXJoYXBzLCB3ZSBu ZWVkIGl0LgoKPgo+IElmIGVuYWJsaW5nIHBsbHJlZl9jbGsgZG9lc24ndCBhY3R1YWxseSBlbmFi bGUgdGhlIDI3bSBjbG9jayBpbnB1dCB0bwo+IHRoZSBtaXBpIGRzaSBjb3JlIGJlY2F1c2UgaXQg aXMgc3RpbGwgZ2F0ZWQgYnkgaHNpX3R4LCBtYXliZSB0aGUgY2xvY2sKPiB0cmVlIHNob3VsZCBi ZSBmaXhlZCBhbmQgaHNpX3R4IHR1cm5lZCBpbnRvIG11bHRpcGxlCj4gaW14X2Nsa19nYXRlMl9z aGFyZWQgY2xvY2tzLgoKQWNjb3JkaW5nIHRvIHRoZSBDQ00gY2hhcHRlciwgdGhlIHZpZGVvXzI3 bSBjbG9jayBpcyBnYXRlZCBieSB0aGUgaHNpX3R4CmNsb2NrLiAgWW91IG1lbnRpb25lZCB0aGlz IGFib3ZlLCBhcyB3ZWxsLgoKPgo+PiArCj4+ICsJZHNpLT5jZmdfY2xrID0gZGV2bV9jbGtfZ2V0 KGRldiwgImNvcmVfY2ZnIik7Cj4+ICsJaWYgKElTX0VSUihkc2ktPmNmZ19jbGspKSB7Cj4+ICsJ CXJldCA9IFBUUl9FUlIoZHNpLT5jZmdfY2xrKTsKPj4gKwkJZGV2X2VycihkZXYsICJVbmFibGUg dG8gZ2V0IGNvbmZpZ3VyYXRpb24gY2xvY2s6ICVkXG4iLCByZXQpOwo+Cj4gQW5kIGxlYXZlIHBs bHJlZiBlbmFibGVkPwoKQXMgSSBtZW50aW9uZWQgaW4gdGhlIHYxLT4gdjIgY2hhbmdlIGxvZywg SSBlbmFibGUvZGlzYWJsZSB0aGUgCnBsbHJlZl9jbGsgYW5kIHBsbHJlZl9nYXRlX2NsayBhdCB0 aGUgY29tcG9uZW50IGJpbmRpbmcvdW5iaW5kaW5nIHN0YWdlcyAKdG8gaGVscCByZW1vdmUgdGhl IGZsYWcgJ2VuYWJsZWQnIGludHJvZHVjZWQgaW4gdjEuCgpJIHJlZmVycmVkIHRvIHRoZSBpLk1Y IEhETUkgZHJpdmVyIHdoaWNoIGVuYWJsZXMvZGlzYWJsZXMgdGhlIGlzZnIgY2xvY2sgCmFuZCB0 aGUgaWFoYiBjbG9jayBhdCB0aGUgY29tcG9uZW50IGJpbmRpbmcvdW5iaW5kaW5nIHN0YWdlcy4K CkkgbWF5IHRyeSB0byBoYW5kbGUgdGhlIGNsb2NrIGVuYWJsZW1lbnQvZGlzYWJsZW1lbnQgbW9y ZSBkZWNlbnRseSBhbmQKYXZvaWQgdXNpbmcgdGhlIGZsYWcgJ2VuYWJsZScuCgo+Cj4+ICsJCXJl dHVybiByZXQ7Cj4+ICsJfQo+PiArCj4+ICsJY2xrX3ByZXBhcmVfZW5hYmxlKGRzaS0+Y2ZnX2Ns ayk7Cj4+ICsJdmFsID0gZHNpX3JlYWQoZHNpLCBEU0lfVkVSU0lPTik7Cj4+ICsJY2xrX2Rpc2Fi bGVfdW5wcmVwYXJlKGRzaS0+Y2ZnX2Nsayk7Cj4+ICsKPj4gKwlkZXZfaW5mbyhkZXYsICJ2ZXJz aW9uIG51bWJlciBpcyAweCUwOHhcbiIsIHZhbCk7Cj4+ICsKPj4gKwlyZXQgPSBpbXhfbWlwaV9k c2lfcmVnaXN0ZXIoZHJtLCBkc2kpOwo+PiArCWlmIChyZXQpCj4KPiBTYW1lIGhlcmUuCgpZb3Ug bWVhbnQgdGhhdCB0aGUgcGxscmVmX2dhdGUgY2xvY2sgaXMgbGVmdCBlbmFibGVkIGFib3ZlLCBy aWdodD8KClJlZ2FyZHMsCkxpdSBZaW5nCgo+Cj4+ICsJCXJldHVybiByZXQ7Cj4+ICsKPj4gKwlk ZXZfc2V0X2RydmRhdGEoZGV2LCBkc2kpOwo+PiArCj4+ICsJcmV0dXJuIG1pcGlfZHNpX2hvc3Rf cmVnaXN0ZXIoJmRzaS0+ZHNpX2hvc3QpOwo+PiArfQo+IFsuLi5dCj4KPiByZWdhcmRzCj4gUGhp bGlwcAo+Cl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRy aS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRw Oi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752044AbaLSFtK (ORCPT ); Fri, 19 Dec 2014 00:49:10 -0500 Received: from mail-by2on0108.outbound.protection.outlook.com ([207.46.100.108]:62368 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751871AbaLSFtI (ORCPT ); Fri, 19 Dec 2014 00:49:08 -0500 Message-ID: <5493BD52.8070804@freescale.com> Date: Fri, 19 Dec 2014 13:53:22 +0800 From: Liu Ying User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Philipp Zabel CC: , , , , , , , , , Subject: Re: [PATCH RFC v2 08/14] drm: imx: Add MIPI DSI host controller driver References: <1418886696-11636-1-git-send-email-Ying.Liu@freescale.com> <1418886696-11636-9-git-send-email-Ying.Liu@freescale.com> <1418902740.4212.46.camel@pengutronix.de> In-Reply-To: <1418902740.4212.46.camel@pengutronix.de> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Ying.Liu@freescale.com; X-Forefront-Antispam-Report: CIP:192.88.158.2;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(339900001)(479174004)(24454002)(189002)(51704005)(199003)(377454003)(57704003)(97736003)(31966008)(59896002)(120916001)(107046002)(81156004)(105606002)(106466001)(77096005)(2950100001)(68736005)(54356999)(50986999)(76176999)(65816999)(62966003)(77156002)(86362001)(21056001)(36756003)(33656002)(99396003)(92566001)(19580405001)(19580395003)(6806004)(80316001)(83506001)(69596002)(84676001)(64126003)(64706001)(87936001)(20776003)(47776003)(65806001)(85426001)(46102003)(4396001)(110136001)(104016003)(50466002)(23676002)(217873001);DIR:OUT;SFP:1102;SCL:1;SRVR:BY2PR0301MB0631;H:az84smr01.freescale.net;FPR:;SPF:Fail;MLV:sfv;PTR:InfoDomainNonexistent;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY2PR0301MB0631; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004);SRVR:BY2PR0301MB0631; X-Forefront-PRVS: 0430FA5CB7 X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:BY2PR0301MB0631; X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2014 05:49:04.8619 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d;Ip=[192.88.158.2] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR0301MB0631 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/18/2014 07:39 PM, Philipp Zabel wrote: > Am Donnerstag, den 18.12.2014, 15:11 +0800 schrieb Liu Ying: >> This patch adds i.MX MIPI DSI host controller driver support. >> Currently, the driver supports the burst with sync pulses mode only. >> >> Signed-off-by: Liu Ying >> --- >> v1->v2: >> * Address almost all comments from Thierry Reding and Russell. >> * Update the DT documentation to remove the display-timings node in the panel node. >> * Update the DT documentation to state that the nodes which represent the possible >> DRM CRTCs the controller may connect with should be placed in the node "ports". >> * Remove the flag 'enabled' from the struct imx_mipi_dsi. >> * Move the format_to_bpp() function in v1 to the common DRM MIPI DSI driver. >> * Improve the way we wait for check status for DPHY and command packet transfer. >> * Improve the DPMS support for the encoder. >> * Split the functions of ->host_attach() and ->mode_valid() clearly as suggested by >> Thierry Reding. >> * Improve the logics in imx_mipi_dsi_dcs_long_write(). >> * Enable/disable the pllref_clk and pllref_gate_clk at the component binding/unbinding >> stages to help remove the flag 'enabled'. >> * Update the module license to be "GPL". >> * Other minor changes, such as coding style issues and macro naming issues. >> >> .../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++ >> drivers/gpu/drm/imx/Kconfig | 6 + >> drivers/gpu/drm/imx/Makefile | 1 + >> drivers/gpu/drm/imx/imx-mipi-dsi.c | 1056 ++++++++++++++++++++ >> 4 files changed, 1141 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt >> create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c >> >> diff --git a/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt >> new file mode 100644 >> index 0000000..892ed62 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt >> @@ -0,0 +1,78 @@ >> +Device-Tree bindings for MIPI DSI host controller >> + >> +MIPI DSI host controller >> +======================== >> + >> +The MIPI DSI host controller is a Synopsys DesignWare IP. >> +It is a digital core that implements all protocol functions defined >> +in the MIPI DSI specification, providing an interface between the >> +system and the MIPI DPHY, and allowing communication with a MIPI DSI >> +compliant display. >> + >> +Required properties: >> + - #address-cells: Should be <1>. >> + - #size-cells: Should be <0>. >> + - compatible: Should be "fsl,imx6q-mipi-dsi" for i.MX6q/sdl SoCs. > > If this is a Synopsys DesignWare IP core as the HDMI TX, I think the > compatible should reflect that. How about a second compatible > "snps,dw-mipi-dsi"? Ok, I'll add this second compatible string. > >> + - reg: Physical base address of the controller and length of memory >> + mapped region. >> + - interrupts: The controller's interrupt number to the CPU(s). >> + - gpr: Should be <&gpr>. >> + The phandle points to the iomuxc-gpr region containing the >> + multiplexer control register for the controller. >> + - clocks, clock-names: Phandles to the controller pllref, pllref_gate >> + and core_cfg clocks, as described in [1] and [2]. >> + >> +Required sub-nodes: >> + - ports: This node may contain up to four port nodes with endpoint >> + definitions as defined in [3], corresponding to the four inputs to >> + the controller multiplexer. >> + - A node to represent a DSI peripheral as described in [4]. >> + >> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt >> +[2] Documentation/devicetree/bindings/clock/imx6q-clock.txt >> +[3] Documentation/devicetree/bindings/media/video-interfaces.txt >> +[4] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt >> + >> +example: >> + gpr: iomuxc-gpr@020e0000 { >> + /* ... */ >> + }; >> + >> + mipi_dsi: mipi@021e0000 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "fsl,imx6q-mipi-dsi"; >> + reg = <0x021e0000 0x4000>; >> + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; >> + gpr = <&gpr>; >> + clocks = <&clks IMX6QDL_CLK_VIDEO_27M>, >> + <&clks IMX6QDL_CLK_HSI_TX>, >> + <&clks IMX6QDL_CLK_HSI_TX>; >> + clock-names = "pllref", "pllref_gate", "core_cfg"; > > Not sure about this. Are those names from the Synopsys documentation? No, I don't think it's from there. > > According to Table 41-1 in the i.MX6Q Reference Manual, this module has > 6 clock inputs: > - ac_clk_125m (from ahb_clk_root) > - pixel_clk (from axi_clk_root) > - cfg_clk and pll_refclk (from video_27m) > - ips_clk and ipg_clk_s (from ipg_clk_root) > The CCM chapter says that of these, "ac_clk_125m", "cfg_clk", ips_clk", > and "pll_refclk" are gated by a single bit called > "mipi_core_cfg_clk_enable", that is clk[CLK_HSI_TX]. > If that is correct, I see no reason for the "pllref_gate" clock. > I suppose two clocks "pllref" and "cfg" should suffice. Using the two clocks makes the code look like this, perhaps: clocks = <&clks IMX6QDL_CLK_VIDEO_27M>, <&clks IMX6QDL_CLK_HSI_TX>; clock-names = "pllref", "core_cfg"; Then, it seems that I have no way to disable the pllref clock if using the clock tree after applying this patch set? Or, perhaps, this one? clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_HSI_TX>; clock-names = "pllref", "core_cfg"; This only uses the gate clock hsi_tx. The current clock tree states that it comes from: pll3_120m -> | -> hsi_tx_sel -> hsi_tx_podf -> hsi_tx pll2_pfd2_396m -> So, I can not get the correct pllref clock frequency with this tree. The pllref clock should be derived from the video_27m clock. The way I decided to use the three clocks is: 1) PLL related * pllref clock only cares about the pll reference rate(the frequency). And, the frequency does matter as it has an impact on the lane clock frequency. * pllref_gate is a gate clock and it only cares about the gate. 2) register configuration related * core_cfg is a gate clock and it only cares about the gate. Usually, the register configuration clock frequency is not so important and the gate is what we really need. I am currently not strong on the way I used. I am open to any better solution. > > Maybe HSI_TX should be split up into multiple shared gate clocks that > all set the mipi_core_cfg clock bits (see below). Yes, maybe. If that's the case, do we need to add two gate clocks in the DT node to represent cfg_gate and pllref_gate respectively? > >> diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig >> index 82fb758..03f04fb 100644 >> --- a/drivers/gpu/drm/imx/Kconfig >> +++ b/drivers/gpu/drm/imx/Kconfig >> @@ -51,3 +51,9 @@ config DRM_IMX_HDMI >> depends on DRM_IMX >> help >> Choose this if you want to use HDMI on i.MX6. >> + >> +config DRM_IMX_MIPI_DSI >> + tristate "Freescale i.MX DRM MIPI DSI" >> + depends on DRM_IMX && MFD_SYSCON >> + help >> + Choose this if you want to use MIPI DSI on i.MX6. >> diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile >> index 582c438..4571d52 100644 >> --- a/drivers/gpu/drm/imx/Makefile >> +++ b/drivers/gpu/drm/imx/Makefile >> @@ -10,3 +10,4 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o >> imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o >> obj-$(CONFIG_DRM_IMX_IPUV3) += imx-ipuv3-crtc.o >> obj-$(CONFIG_DRM_IMX_HDMI) += imx-hdmi.o >> +obj-$(CONFIG_DRM_IMX_MIPI_DSI) += imx-mipi-dsi.o >> diff --git a/drivers/gpu/drm/imx/imx-mipi-dsi.c b/drivers/gpu/drm/imx/imx-mipi-dsi.c >> new file mode 100644 >> index 0000000..1cb4328 >> --- /dev/null >> +++ b/drivers/gpu/drm/imx/imx-mipi-dsi.c > [...] >> +static int imx_mipi_dsi_bind(struct device *dev, struct device *master, void *data) >> +{ >> + struct platform_device *pdev = to_platform_device(dev); >> + struct drm_device *drm = data; >> + struct device_node *np = dev->of_node; >> + struct imx_mipi_dsi *dsi; >> + struct resource *res; >> + u32 val; >> + int ret; >> + >> + dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); >> + if (!dsi) >> + return -ENOMEM; >> + >> + dsi->dev = dev; >> + dsi->dsi_host.ops = &imx_mipi_dsi_host_ops; >> + dsi->dsi_host.dev = dev; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + dsi->base = devm_ioremap_resource(dev, res); >> + if (IS_ERR(dsi->base)) >> + return PTR_ERR(dsi->base); >> + >> + dsi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); >> + if (IS_ERR(dsi->regmap)) >> + return PTR_ERR(dsi->regmap); >> + >> + dsi->pllref_clk = devm_clk_get(dev, "pllref"); >> + if (IS_ERR(dsi->pllref_clk)) { >> + ret = PTR_ERR(dsi->pllref_clk); >> + dev_err(dev, "Unable to get pll reference clock: %d\n", ret); >> + return ret; >> + } >> + clk_prepare_enable(dsi->pllref_clk); >> + >> + dsi->pllref_gate_clk = devm_clk_get(dev, "pllref_gate"); >> + if (IS_ERR(dsi->pllref_gate_clk)) { >> + ret = PTR_ERR(dsi->pllref_gate_clk); >> + dev_err(dev, "Unable to get pll reference gate clock: %d\n", ret); >> + return ret; >> + } >> + clk_prepare_enable(dsi->pllref_gate_clk); > > As said above, I don't think this clock is needed, or is it? Perhaps, we need it. > > If enabling pllref_clk doesn't actually enable the 27m clock input to > the mipi dsi core because it is still gated by hsi_tx, maybe the clock > tree should be fixed and hsi_tx turned into multiple > imx_clk_gate2_shared clocks. According to the CCM chapter, the video_27m clock is gated by the hsi_tx clock. You mentioned this above, as well. > >> + >> + dsi->cfg_clk = devm_clk_get(dev, "core_cfg"); >> + if (IS_ERR(dsi->cfg_clk)) { >> + ret = PTR_ERR(dsi->cfg_clk); >> + dev_err(dev, "Unable to get configuration clock: %d\n", ret); > > And leave pllref enabled? As I mentioned in the v1-> v2 change log, I enable/disable the pllref_clk and pllref_gate_clk at the component binding/unbinding stages to help remove the flag 'enabled' introduced in v1. I referred to the i.MX HDMI driver which enables/disables the isfr clock and the iahb clock at the component binding/unbinding stages. I may try to handle the clock enablement/disablement more decently and avoid using the flag 'enable'. > >> + return ret; >> + } >> + >> + clk_prepare_enable(dsi->cfg_clk); >> + val = dsi_read(dsi, DSI_VERSION); >> + clk_disable_unprepare(dsi->cfg_clk); >> + >> + dev_info(dev, "version number is 0x%08x\n", val); >> + >> + ret = imx_mipi_dsi_register(drm, dsi); >> + if (ret) > > Same here. You meant that the pllref_gate clock is left enabled above, right? Regards, Liu Ying > >> + return ret; >> + >> + dev_set_drvdata(dev, dsi); >> + >> + return mipi_dsi_host_register(&dsi->dsi_host); >> +} > [...] > > regards > Philipp >