From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ying.Liu@freescale.com (Liu Ying) Date: Fri, 19 Dec 2014 15:46:23 +0800 Subject: [PATCH RFC v2 00/14] Add support for i.MX MIPI DSI DRM driver In-Reply-To: <59cf2641.8c29.14a614058be.Coremail.andyshrk@163.com> References: <1418886696-11636-1-git-send-email-Ying.Liu@freescale.com> <59cf2641.8c29.14a614058be.Coremail.andyshrk@163.com> Message-ID: <5493D7CF.1020304@freescale.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Andy, On 12/19/2014 02:33 PM, Andy Yan wrote: > Hi Liu Ying: > > I foud Rockchip RK618 (a mfd function device with mipi dsi?lvds > transmitter?HDMI TX?and audio codec?and > controlled by the SOC from i2c ) have the same register layout with your > i.MX MIPI DSI?which means RK618 MIPI > DSI also have the Synopsys compatible DSI IP?So Would you please make > this drives more platform independent? > I may try to place the Synopsys DesignWare MIPI DSI driver in the drm/bridge directory and make it as less platform-dependant as possible. I have no access to the Rockchip RK618 chip and it's reference menu. You probably may add the Rockchip part support later. Regards, Liu Ying > > > > At 2014-12-18 15:11:22, "Liu Ying" wrote: >>Hi, >> >>This series addressed almost all comments from Thierry Redding and Russell >>on v1. >> >>This series adds support for i.MX MIPI DSI DRM driver. >>Currently, the MIPI DSI driver only supports the burst with sync pulse mode. >> >>This series also includes a DRM panel driver for the Truly TFT480800-16-E panel >>which is driven by the Himax HX8369A driver IC. The driver IC data sheet could >>be found at [1]. As mentioned by the data sheet, the driver IC supports several >>interface modes. Currently, the DRM panel driver only supports the MIPI DSI video >>mode. New interface modes could be added later(perhaps, just like the way the DRM >>simple panel driver supports both MIPI DSI interface panels and simple(parallel) >>interface panels). >> >>The MIPI DSI feature is tested on i.MX6Q SabreSD board and i.MX6DL SabreSD board. >>The MIPI DSI display could be enabled directly on i.MX6Q SabreSD board after >>applying this series, because the 26.4MHz pixel clock the panel requires could be >>derived from the IPU HSP clock(264MHz) with an integer divider. >>On i.MX6DL SabreSD board, we need to manually disable the LVDS and HDMI displays in >>the device tree blob, since the i.MX6DL IPU HSP clock is 198MHz at present, which >>makes the pixel clock share the PLL5 video clock source with the LVDS and HDMI, >>thus, the panel cannot get the pixel clock rate it wants. >> >>Patch 01/15 is needed to get a precise pixel clock rate(26.4MHz) from the PLL5 video >>clock. If we don't have this patch, the pixel clock rate is about 20MHz, which >>causes a horitonal shift on the display image. >> >>This series can be applied on the drm-next branch. >> >>[1] http://www.allshore.com/pdf/Himax_HX8369-A.pdf >> >>Liu Ying (14): >> clk: divider: Correct parent clk round rate if no bestdiv is normally >> found >> of: Add vendor prefix for Himax Technologies Inc. >> of: Add vendor prefix for Truly Semiconductors Limited >> ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits >> definition >> ARM: imx6q: clk: Add the video_27m clock >> ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' >> node >> drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format >> drm: imx: Add MIPI DSI host controller driver >> drm: panel: Add support for Himax HX8369A MIPI DSI panel >> ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller >> ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI >> DSI panel >> ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of >> staging >> ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller >> ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel >> >> .../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++ >> .../devicetree/bindings/panel/himax,hx8369a.txt | 41 + >> .../devicetree/bindings/vendor-prefixes.txt | 2 + >> arch/arm/boot/dts/imx6q.dtsi | 20 +- >> arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20 + >> arch/arm/boot/dts/imx6qdl.dtsi | 30 +- >> arch/arm/configs/imx_v6_v7_defconfig | 17 +- >> arch/arm/mach-imx/clk-imx6q.c | 1 + >> drivers/clk/clk-divider.c | 3 +- >> drivers/gpu/drm/imx/Kconfig | 6 + >> drivers/gpu/drm/imx/Makefile | 1 + >> drivers/gpu/drm/imx/imx-mipi-dsi.c | 1056 ++++++++++++++++++++ >> drivers/gpu/drm/panel/Kconfig | 5 + >> drivers/gpu/drm/panel/Makefile | 1 + >> drivers/gpu/drm/panel/panel-himax-hx8369a.c | 573 +++++++++++ >> include/drm/drm_mipi_dsi.h | 14 + >> include/dt-bindings/clock/imx6qdl-clock.h | 3 +- >> include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + >> 18 files changed, 1844 insertions(+), 28 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt >> create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt >> create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c >> create mode 100644 drivers/gpu/drm/panel/panel-himax-hx8369a.c >> >>-- >>2.1.0 >> >>_______________________________________________ >>dri-devel mailing list >>dri-devel at lists.freedesktop.org >>http://lists.freedesktop.org/mailman/listinfo/dri-devel > > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Liu Ying Subject: Re: [PATCH RFC v2 00/14] Add support for i.MX MIPI DSI DRM driver Date: Fri, 19 Dec 2014 15:46:23 +0800 Message-ID: <5493D7CF.1020304@freescale.com> References: <1418886696-11636-1-git-send-email-Ying.Liu@freescale.com> <59cf2641.8c29.14a614058be.Coremail.andyshrk@163.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <59cf2641.8c29.14a614058be.Coremail.andyshrk@163.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Andy Yan Cc: devicetree@vger.kernel.org, mturquette@linaro.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@pengutronix.de, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org SGkgQW5keSwKCk9uIDEyLzE5LzIwMTQgMDI6MzMgUE0sIEFuZHkgWWFuIHdyb3RlOgo+IEhpIExp dSBZaW5nOgo+Cj4gICBJIGZvdWQgUm9ja2NoaXAgUks2MTggKGEgbWZkIGZ1bmN0aW9uIGRldmlj ZSB3aXRoIG1pcGkgZHNp77yMbHZkcwo+IHRyYW5zbWl0dGVy44CBSERNSSBUWOOAgWFuZCBhdWRp byBjb2RlY++8jGFuZAo+IGNvbnRyb2xsZWQgYnkgdGhlIFNPQyBmcm9tIGkyYyApIGhhdmUgdGhl IHNhbWUgcmVnaXN0ZXIgbGF5b3V0IHdpdGggeW91cgo+IGkuTVggTUlQSSBEU0nvvIx3aGljaCBt ZWFucyBSSzYxOCBNSVBJCj4gRFNJIGFsc28gaGF2ZSB0aGUgU3lub3BzeXMgY29tcGF0aWJsZSBE U0kgSVDjgIJTbyBXb3VsZCB5b3UgcGxlYXNlIG1ha2UKPiB0aGlzIGRyaXZlcyBtb3JlIHBsYXRm b3JtIGluZGVwZW5kZW5077yfCj4KCkkgbWF5IHRyeSB0byBwbGFjZSB0aGUgU3lub3BzeXMgRGVz aWduV2FyZSBNSVBJIERTSSBkcml2ZXIgaW4gdGhlCmRybS9icmlkZ2UgZGlyZWN0b3J5IGFuZCBt YWtlIGl0IGFzIGxlc3MgcGxhdGZvcm0tZGVwZW5kYW50IGFzCnBvc3NpYmxlLgoKSSBoYXZlIG5v IGFjY2VzcyB0byB0aGUgUm9ja2NoaXAgUks2MTggY2hpcCBhbmQgaXQncyByZWZlcmVuY2UgbWVu dS4KWW91IHByb2JhYmx5IG1heSBhZGQgdGhlIFJvY2tjaGlwIHBhcnQgc3VwcG9ydCBsYXRlci4K ClJlZ2FyZHMsCkxpdSBZaW5nCgo+Cj4KPgo+IEF0IDIwMTQtMTItMTggMTU6MTE6MjIsICJMaXUg WWluZyIgPFlpbmcuTGl1QGZyZWVzY2FsZS5jb20+IHdyb3RlOgo+PkhpLAo+Pgo+PlRoaXMgc2Vy aWVzIGFkZHJlc3NlZCBhbG1vc3QgYWxsIGNvbW1lbnRzIGZyb20gVGhpZXJyeSBSZWRkaW5nIGFu ZCBSdXNzZWxsCj4+b24gdjEuCj4+Cj4+VGhpcyBzZXJpZXMgYWRkcyBzdXBwb3J0IGZvciBpLk1Y IE1JUEkgRFNJIERSTSBkcml2ZXIuCj4+Q3VycmVudGx5LCB0aGUgTUlQSSBEU0kgZHJpdmVyIG9u bHkgc3VwcG9ydHMgdGhlIGJ1cnN0IHdpdGggc3luYyBwdWxzZSBtb2RlLgo+Pgo+PlRoaXMgc2Vy aWVzIGFsc28gaW5jbHVkZXMgYSBEUk0gcGFuZWwgZHJpdmVyIGZvciB0aGUgVHJ1bHkgVEZUNDgw ODAwLTE2LUUgcGFuZWwKPj53aGljaCBpcyBkcml2ZW4gYnkgdGhlIEhpbWF4IEhYODM2OUEgZHJp dmVyIElDLiAgVGhlIGRyaXZlciBJQyBkYXRhIHNoZWV0IGNvdWxkCj4+YmUgZm91bmQgYXQgWzFd LiAgQXMgbWVudGlvbmVkIGJ5IHRoZSBkYXRhIHNoZWV0LCB0aGUgZHJpdmVyIElDIHN1cHBvcnRz IHNldmVyYWwKPj5pbnRlcmZhY2UgbW9kZXMuICBDdXJyZW50bHksIHRoZSBEUk0gcGFuZWwgZHJp dmVyIG9ubHkgc3VwcG9ydHMgdGhlIE1JUEkgRFNJIHZpZGVvCj4+bW9kZS4gIE5ldyBpbnRlcmZh Y2UgbW9kZXMgY291bGQgYmUgYWRkZWQgbGF0ZXIocGVyaGFwcywganVzdCBsaWtlIHRoZSB3YXkg dGhlIERSTQo+PnNpbXBsZSBwYW5lbCBkcml2ZXIgc3VwcG9ydHMgYm90aCBNSVBJIERTSSBpbnRl cmZhY2UgcGFuZWxzIGFuZCBzaW1wbGUocGFyYWxsZWwpCj4+aW50ZXJmYWNlIHBhbmVscykuCj4+ Cj4+VGhlIE1JUEkgRFNJIGZlYXR1cmUgaXMgdGVzdGVkIG9uIGkuTVg2USBTYWJyZVNEIGJvYXJk IGFuZCBpLk1YNkRMIFNhYnJlU0QgYm9hcmQuCj4+VGhlIE1JUEkgRFNJIGRpc3BsYXkgY291bGQg YmUgZW5hYmxlZCBkaXJlY3RseSBvbiBpLk1YNlEgU2FicmVTRCBib2FyZCBhZnRlcgo+PmFwcGx5 aW5nIHRoaXMgc2VyaWVzLCBiZWNhdXNlIHRoZSAyNi40TUh6IHBpeGVsIGNsb2NrIHRoZSBwYW5l bCByZXF1aXJlcyBjb3VsZCBiZQo+PmRlcml2ZWQgZnJvbSB0aGUgSVBVIEhTUCBjbG9jaygyNjRN SHopIHdpdGggYW4gaW50ZWdlciBkaXZpZGVyLgo+Pk9uIGkuTVg2REwgU2FicmVTRCBib2FyZCwg d2UgbmVlZCB0byBtYW51YWxseSBkaXNhYmxlIHRoZSBMVkRTIGFuZCBIRE1JIGRpc3BsYXlzIGlu Cj4+dGhlIGRldmljZSB0cmVlIGJsb2IsIHNpbmNlIHRoZSBpLk1YNkRMIElQVSBIU1AgY2xvY2sg aXMgMTk4TUh6IGF0IHByZXNlbnQsIHdoaWNoCj4+bWFrZXMgdGhlIHBpeGVsIGNsb2NrIHNoYXJl IHRoZSBQTEw1IHZpZGVvIGNsb2NrIHNvdXJjZSB3aXRoIHRoZSBMVkRTIGFuZCBIRE1JLAo+PnRo dXMsIHRoZSBwYW5lbCBjYW5ub3QgZ2V0IHRoZSBwaXhlbCBjbG9jayByYXRlIGl0IHdhbnRzLgo+ Pgo+PlBhdGNoIDAxLzE1IGlzIG5lZWRlZCB0byBnZXQgYSBwcmVjaXNlIHBpeGVsIGNsb2NrIHJh dGUoMjYuNE1IeikgZnJvbSB0aGUgUExMNSB2aWRlbwo+PmNsb2NrLiAgSWYgd2UgZG9uJ3QgaGF2 ZSB0aGlzIHBhdGNoLCB0aGUgcGl4ZWwgY2xvY2sgcmF0ZSBpcyBhYm91dCAyME1Ieiwgd2hpY2gK Pj5jYXVzZXMgYSBob3JpdG9uYWwgc2hpZnQgb24gdGhlIGRpc3BsYXkgaW1hZ2UuCj4+Cj4+VGhp cyBzZXJpZXMgY2FuIGJlIGFwcGxpZWQgb24gdGhlIGRybS1uZXh0IGJyYW5jaC4KPj4KPj5bMV0g aHR0cDovL3d3dy5hbGxzaG9yZS5jb20vcGRmL0hpbWF4X0hYODM2OS1BLnBkZgo+Pgo+PkxpdSBZ aW5nICgxNCk6Cj4+ICBjbGs6IGRpdmlkZXI6IENvcnJlY3QgcGFyZW50IGNsayByb3VuZCByYXRl IGlmIG5vIGJlc3RkaXYgaXMgbm9ybWFsbHkKPj4gICAgZm91bmQKPj4gIG9mOiBBZGQgdmVuZG9y IHByZWZpeCBmb3IgSGltYXggVGVjaG5vbG9naWVzIEluYy4KPj4gIG9mOiBBZGQgdmVuZG9yIHBy ZWZpeCBmb3IgVHJ1bHkgU2VtaWNvbmR1Y3RvcnMgTGltaXRlZAo+PiAgQVJNOiBpbXg2cTogQWRk IEdQUjMgTUlQSSBtdXhpbmcgY29udHJvbCByZWdpc3RlciBmaWVsZCBzaGlmdCBiaXRzCj4+ICAg IGRlZmluaXRpb24KPj4gIEFSTTogaW14NnE6IGNsazogQWRkIHRoZSB2aWRlb18yN20gY2xvY2sK Pj4gIEFSTTogZHRzOiBpbXg2cWRsOiBNb3ZlIGV4aXN0aW5nIE1JUEkgRFNJIHBvcnRzIGludG8g YSBuZXcgJ3BvcnRzJwo+PiAgICBub2RlCj4+ICBkcm0vZHNpOiBBZGQgYSBoZWxwZXIgdG8gZ2V0 IGJpdHMgcGVyIHBpeGVsIG9mIE1JUEkgRFNJIHBpeGVsIGZvcm1hdAo+PiAgZHJtOiBpbXg6IEFk ZCBNSVBJIERTSSBob3N0IGNvbnRyb2xsZXIgZHJpdmVyCj4+ICBkcm06IHBhbmVsOiBBZGQgc3Vw cG9ydCBmb3IgSGltYXggSFg4MzY5QSBNSVBJIERTSSBwYW5lbAo+PiAgQVJNOiBkdHNpOiBpbXg2 cWRsOiBBZGQgc3VwcG9ydCBmb3IgTUlQSSBEU0kgaG9zdCBjb250cm9sbGVyCj4+ICBBUk06IGR0 czogaW14NnFkbC1zYWJyZXNkOiBBZGQgc3VwcG9ydCBmb3IgVFJVTFkgVEZUNDgwODAwLTE2LUUg TUlQSQo+PiAgICBEU0kgcGFuZWwKPj4gIEFSTTogaW14X3Y2X3Y3X2RlZmNvbmZpZzogQ2xlYW51 cCBmb3IgaW14IGRybSBiZWluZyBtb3ZlZCBvdXQgb2YKPj4gICAgc3RhZ2luZwo+PiAgQVJNOiBp bXhfdjZfdjdfZGVmY29uZmlnOiBBZGQgc3VwcG9ydCBmb3IgTUlQSSBEU0kgaG9zdCBjb250cm9s bGVyCj4+ICBBUk06IGlteF92Nl92N19kZWZjb25maWc6IEFkZCBzdXBwb3J0IGZvciBIaW1heCBI WDgzNjlBIHBhbmVsCj4+Cj4+IC4uLi9kZXZpY2V0cmVlL2JpbmRpbmdzL2RybS9pbXgvbWlwaV9k c2kudHh0ICAgICAgIHwgICA3OCArKwo+PiAuLi4vZGV2aWNldHJlZS9iaW5kaW5ncy9wYW5lbC9o aW1heCxoeDgzNjlhLnR4dCAgICB8ICAgNDEgKwo+PiAuLi4vZGV2aWNldHJlZS9iaW5kaW5ncy92 ZW5kb3ItcHJlZml4ZXMudHh0ICAgICAgICB8ICAgIDIgKwo+PiBhcmNoL2FybS9ib290L2R0cy9p bXg2cS5kdHNpICAgICAgICAgICAgICAgICAgICAgICB8ICAgMjAgKy0KPj4gYXJjaC9hcm0vYm9v dC9kdHMvaW14NnFkbC1zYWJyZXNkLmR0c2kgICAgICAgICAgICAgfCAgIDIwICsKPj4gYXJjaC9h cm0vYm9vdC9kdHMvaW14NnFkbC5kdHNpICAgICAgICAgICAgICAgICAgICAgfCAgIDMwICstCj4+ IGFyY2gvYXJtL2NvbmZpZ3MvaW14X3Y2X3Y3X2RlZmNvbmZpZyAgICAgICAgICAgICAgIHwgICAx NyArLQo+PiBhcmNoL2FybS9tYWNoLWlteC9jbGstaW14NnEuYyAgICAgICAgICAgICAgICAgICAg ICB8ICAgIDEgKwo+PiBkcml2ZXJzL2Nsay9jbGstZGl2aWRlci5jICAgICAgICAgICAgICAgICAg ICAgICAgICB8ICAgIDMgKy0KPj4gZHJpdmVycy9ncHUvZHJtL2lteC9LY29uZmlnICAgICAgICAg ICAgICAgICAgICAgICAgfCAgICA2ICsKPj4gZHJpdmVycy9ncHUvZHJtL2lteC9NYWtlZmlsZSAg ICAgICAgICAgICAgICAgICAgICAgfCAgICAxICsKPj4gZHJpdmVycy9ncHUvZHJtL2lteC9pbXgt bWlwaS1kc2kuYyAgICAgICAgICAgICAgICAgfCAxMDU2ICsrKysrKysrKysrKysrKysrKysrCj4+ IGRyaXZlcnMvZ3B1L2RybS9wYW5lbC9LY29uZmlnICAgICAgICAgICAgICAgICAgICAgIHwgICAg NSArCj4+IGRyaXZlcnMvZ3B1L2RybS9wYW5lbC9NYWtlZmlsZSAgICAgICAgICAgICAgICAgICAg IHwgICAgMSArCj4+IGRyaXZlcnMvZ3B1L2RybS9wYW5lbC9wYW5lbC1oaW1heC1oeDgzNjlhLmMg ICAgICAgIHwgIDU3MyArKysrKysrKysrKwo+PiBpbmNsdWRlL2RybS9kcm1fbWlwaV9kc2kuaCAg ICAgICAgICAgICAgICAgICAgICAgICB8ICAgMTQgKwo+PiBpbmNsdWRlL2R0LWJpbmRpbmdzL2Ns b2NrL2lteDZxZGwtY2xvY2suaCAgICAgICAgICB8ICAgIDMgKy0KPj4gaW5jbHVkZS9saW51eC9t ZmQvc3lzY29uL2lteDZxLWlvbXV4Yy1ncHIuaCAgICAgICAgfCAgICAxICsKPj4gMTggZmlsZXMg Y2hhbmdlZCwgMTg0NCBpbnNlcnRpb25zKCspLCAyOCBkZWxldGlvbnMoLSkKPj4gY3JlYXRlIG1v ZGUgMTAwNjQ0IERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kcm0vaW14L21pcGlf ZHNpLnR4dAo+PiBjcmVhdGUgbW9kZSAxMDA2NDQgRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2Jp bmRpbmdzL3BhbmVsL2hpbWF4LGh4ODM2OWEudHh0Cj4+IGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2 ZXJzL2dwdS9kcm0vaW14L2lteC1taXBpLWRzaS5jCj4+IGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2 ZXJzL2dwdS9kcm0vcGFuZWwvcGFuZWwtaGltYXgtaHg4MzY5YS5jCj4+Cj4+LS0KPj4yLjEuMAo+ Pgo+Pl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4+ZHJp LWRldmVsIG1haWxpbmcgbGlzdAo+PmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKPj5o dHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCj4K Pgo+Cl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1k ZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8v bGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752124AbaLSHmJ (ORCPT ); Fri, 19 Dec 2014 02:42:09 -0500 Received: from mail-bn1on0136.outbound.protection.outlook.com ([157.56.110.136]:17985 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751547AbaLSHmH (ORCPT ); Fri, 19 Dec 2014 02:42:07 -0500 Message-ID: <5493D7CF.1020304@freescale.com> Date: Fri, 19 Dec 2014 15:46:23 +0800 From: Liu Ying User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Andy Yan CC: , , , , , , Subject: Re: [PATCH RFC v2 00/14] Add support for i.MX MIPI DSI DRM driver References: <1418886696-11636-1-git-send-email-Ying.Liu@freescale.com> <59cf2641.8c29.14a614058be.Coremail.andyshrk@163.com> In-Reply-To: <59cf2641.8c29.14a614058be.Coremail.andyshrk@163.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Ying.Liu@freescale.com; X-Forefront-Antispam-Report: CIP:192.88.168.50;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(339900001)(189002)(24454002)(479174004)(51704005)(199003)(243025005)(377454003)(377424004)(65816999)(104016003)(21056001)(107046002)(77156002)(4396001)(106466001)(33656002)(15975445007)(6806004)(54356999)(83506001)(1720100001)(47776003)(2950100001)(105606002)(87936001)(68736005)(110136001)(19580405001)(59896002)(19580395003)(36756003)(50986999)(77096005)(62966003)(31966008)(80316001)(65806001)(64706001)(46102003)(65956001)(97736003)(85426001)(99396003)(23676002)(20776003)(64126003)(84676001)(120916001)(76176999)(86362001)(50466002)(87266999)(92566001)(217873001);DIR:OUT;SFP:1102;SCL:1;SRVR:CY1PR0301MB0634;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;MLV:sfv;PTR:InfoDomainNonexistent;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:CY1PR0301MB0634; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004);SRVR:CY1PR0301MB0634; X-Forefront-PRVS: 0430FA5CB7 X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:CY1PR0301MB0634; X-OriginatorOrg: freescale.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andy, On 12/19/2014 02:33 PM, Andy Yan wrote: > Hi Liu Ying: > > I foud Rockchip RK618 (a mfd function device with mipi dsi,lvds > transmitter、HDMI TX、and audio codec,and > controlled by the SOC from i2c ) have the same register layout with your > i.MX MIPI DSI,which means RK618 MIPI > DSI also have the Synopsys compatible DSI IP。So Would you please make > this drives more platform independent? > I may try to place the Synopsys DesignWare MIPI DSI driver in the drm/bridge directory and make it as less platform-dependant as possible. I have no access to the Rockchip RK618 chip and it's reference menu. You probably may add the Rockchip part support later. Regards, Liu Ying > > > > At 2014-12-18 15:11:22, "Liu Ying" wrote: >>Hi, >> >>This series addressed almost all comments from Thierry Redding and Russell >>on v1. >> >>This series adds support for i.MX MIPI DSI DRM driver. >>Currently, the MIPI DSI driver only supports the burst with sync pulse mode. >> >>This series also includes a DRM panel driver for the Truly TFT480800-16-E panel >>which is driven by the Himax HX8369A driver IC. The driver IC data sheet could >>be found at [1]. As mentioned by the data sheet, the driver IC supports several >>interface modes. Currently, the DRM panel driver only supports the MIPI DSI video >>mode. New interface modes could be added later(perhaps, just like the way the DRM >>simple panel driver supports both MIPI DSI interface panels and simple(parallel) >>interface panels). >> >>The MIPI DSI feature is tested on i.MX6Q SabreSD board and i.MX6DL SabreSD board. >>The MIPI DSI display could be enabled directly on i.MX6Q SabreSD board after >>applying this series, because the 26.4MHz pixel clock the panel requires could be >>derived from the IPU HSP clock(264MHz) with an integer divider. >>On i.MX6DL SabreSD board, we need to manually disable the LVDS and HDMI displays in >>the device tree blob, since the i.MX6DL IPU HSP clock is 198MHz at present, which >>makes the pixel clock share the PLL5 video clock source with the LVDS and HDMI, >>thus, the panel cannot get the pixel clock rate it wants. >> >>Patch 01/15 is needed to get a precise pixel clock rate(26.4MHz) from the PLL5 video >>clock. If we don't have this patch, the pixel clock rate is about 20MHz, which >>causes a horitonal shift on the display image. >> >>This series can be applied on the drm-next branch. >> >>[1] http://www.allshore.com/pdf/Himax_HX8369-A.pdf >> >>Liu Ying (14): >> clk: divider: Correct parent clk round rate if no bestdiv is normally >> found >> of: Add vendor prefix for Himax Technologies Inc. >> of: Add vendor prefix for Truly Semiconductors Limited >> ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits >> definition >> ARM: imx6q: clk: Add the video_27m clock >> ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' >> node >> drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format >> drm: imx: Add MIPI DSI host controller driver >> drm: panel: Add support for Himax HX8369A MIPI DSI panel >> ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller >> ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI >> DSI panel >> ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of >> staging >> ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller >> ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel >> >> .../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++ >> .../devicetree/bindings/panel/himax,hx8369a.txt | 41 + >> .../devicetree/bindings/vendor-prefixes.txt | 2 + >> arch/arm/boot/dts/imx6q.dtsi | 20 +- >> arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20 + >> arch/arm/boot/dts/imx6qdl.dtsi | 30 +- >> arch/arm/configs/imx_v6_v7_defconfig | 17 +- >> arch/arm/mach-imx/clk-imx6q.c | 1 + >> drivers/clk/clk-divider.c | 3 +- >> drivers/gpu/drm/imx/Kconfig | 6 + >> drivers/gpu/drm/imx/Makefile | 1 + >> drivers/gpu/drm/imx/imx-mipi-dsi.c | 1056 ++++++++++++++++++++ >> drivers/gpu/drm/panel/Kconfig | 5 + >> drivers/gpu/drm/panel/Makefile | 1 + >> drivers/gpu/drm/panel/panel-himax-hx8369a.c | 573 +++++++++++ >> include/drm/drm_mipi_dsi.h | 14 + >> include/dt-bindings/clock/imx6qdl-clock.h | 3 +- >> include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + >> 18 files changed, 1844 insertions(+), 28 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt >> create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt >> create mode 100644 drivers/gpu/drm/imx/imx-mipi-dsi.c >> create mode 100644 drivers/gpu/drm/panel/panel-himax-hx8369a.c >> >>-- >>2.1.0 >> >>_______________________________________________ >>dri-devel mailing list >>dri-devel@lists.freedesktop.org >>http://lists.freedesktop.org/mailman/listinfo/dri-devel > > >