From mboxrd@z Thu Jan 1 00:00:00 1970 From: Oleksij Rempel Date: Fri, 19 Dec 2014 14:25:14 +0100 Subject: [ath9k-devel] AR9271 Clock rate In-Reply-To: References: Message-ID: <5494273A.4090901@rempel-privat.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: ath9k-devel@lists.ath9k.org Am 19.12.2014 um 10:21 schrieb Adrian Nicolau: > Hello, > > I am using a TL-WN722N for a Wi-Fi ToF project; the SOC is AR9271 and I > obtained the ath9k_htc source code via backports version 3.17.1-1. For > ToF measurements, the higher the clock rate of the SOC, the better, and > I know that AR9271 has a 117 MHz one. > Reading through the code, in file ath/ath9k/hw.c, function > ath9k_hw_set_clockrate [1] there is no entry for AS_SREV_9271, leaving > the clockrate to be 44MHz in the common structure and throughout execution. > The 117MHz setting is done later in the code by writing to a registry [2]. > > I am wondering why the writing to the registry is not reflected in the > common structure as well. > > [1] https://github.com/torvalds/linux/blob/master/drivers/net/wireless/ath/ath9k/hw.c#L39 > [2] https://github.com/torvalds/linux/blob/master/drivers/net/wireless/ath/ath9k/hw.c#L864 Because you are writing to wrong offset. REG_WRITE will do it to a memory region mapped to mac core for this SoC. -- Regards, Oleksij -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 213 bytes Desc: OpenPGP digital signature Url : http://lists.ath9k.org/pipermail/ath9k-devel/attachments/20141219/af5237d3/attachment.pgp