From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Dec 2014 01:43:46 +0100 (CET) Received: from mailapp01.imgtec.com ([195.59.15.196]:19575 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27009080AbaLTAnpgYr-h (ORCPT ); Sat, 20 Dec 2014 01:43:45 +0100 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id C272C367DF6ED; Sat, 20 Dec 2014 00:43:35 +0000 (GMT) Received: from BAMAIL02.ba.imgtec.org (10.20.40.28) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Sat, 20 Dec 2014 00:43:39 +0000 Received: from [192.168.65.146] (192.168.65.146) by bamail02.ba.imgtec.org (10.20.40.28) with Microsoft SMTP Server (TLS) id 14.3.174.1; Fri, 19 Dec 2014 16:43:37 -0800 Message-ID: <5494C639.8050808@imgtec.com> Date: Fri, 19 Dec 2014 16:43:37 -0800 From: Leonid Yegoshin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: David Daney , , CC: David Daney Subject: Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. References: <1419035585-21671-1-git-send-email-ddaney.cavm@gmail.com> In-Reply-To: <1419035585-21671-1-git-send-email-ddaney.cavm@gmail.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.65.146] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 44853 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Leonid.Yegoshin@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On 12/19/2014 04:33 PM, David Daney wrote: > From: David Daney > > The two patches reverted here break eXecute-Inhibit (XI) memory > protection support. Before the patches we get SIGSEGV when attempting > to execute in non-executable memory, after the patches we loop forever > in handle_tlbl. > > It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think > the most prudent thing is to revert these patches, and then only reapply > something that works after it has been well tested. > > David Daney (2): > Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI > exceptions" > Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" > > arch/mips/include/asm/mipsregs.h | 1 - > arch/mips/kernel/cpu-probe.c | 9 --------- > arch/mips/kernel/traps.c | 7 ------- > arch/mips/mm/tlbex.c | 4 ++-- > 4 files changed, 2 insertions(+), 19 deletions(-) > Well, it may be have sense just to fix tlb_init() instead. From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:19575 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27009080AbaLTAnpgYr-h (ORCPT ); Sat, 20 Dec 2014 01:43:45 +0100 Message-ID: <5494C639.8050808@imgtec.com> Date: Fri, 19 Dec 2014 16:43:37 -0800 From: Leonid Yegoshin MIME-Version: 1.0 Subject: Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. References: <1419035585-21671-1-git-send-email-ddaney.cavm@gmail.com> In-Reply-To: <1419035585-21671-1-git-send-email-ddaney.cavm@gmail.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Message-ID: <20141220004337.ka5QNQ48lt9Um1aOzTk3ljYIxI4f7mnn0XefTx0DoWU@z> On 12/19/2014 04:33 PM, David Daney wrote: > From: David Daney > > The two patches reverted here break eXecute-Inhibit (XI) memory > protection support. Before the patches we get SIGSEGV when attempting > to execute in non-executable memory, after the patches we loop forever > in handle_tlbl. > > It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think > the most prudent thing is to revert these patches, and then only reapply > something that works after it has been well tested. > > David Daney (2): > Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI > exceptions" > Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" > > arch/mips/include/asm/mipsregs.h | 1 - > arch/mips/kernel/cpu-probe.c | 9 --------- > arch/mips/kernel/traps.c | 7 ------- > arch/mips/mm/tlbex.c | 4 ++-- > 4 files changed, 2 insertions(+), 19 deletions(-) > Well, it may be have sense just to fix tlb_init() instead.