Re: [PATCH] MIPS: Fix C0_Pagegrain[IEC] support.

[David Daney <ddaney.cavm@gmail.com>]

On 12/19/2014 05:21 PM, Leonid Yegoshin wrote:
> On 12/19/2014 05:15 PM, David Daney wrote:
>> From: David Daney <david.daney@cavium.com>
>>
>> If we are generating TLB exception expecting separate vectors, we must
>> enable the feature.
>>
>> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>> Signed-off-by: David Daney <david.daney@cavium.com>
>> ---
>>
>> Very lightly tested, but it seems to make my XI and RI tests work on
>> OCTEON II CPUs, which have the C0_Pagegrain[IEC] bit.
>>
>>   arch/mips/mm/tlb-r4k.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
>> index e90b2e8..30639a6 100644
>> --- a/arch/mips/mm/tlb-r4k.c
>> +++ b/arch/mips/mm/tlb-r4k.c
>> @@ -489,6 +489,8 @@ static void r4k_tlb_configure(void)
>>   #ifdef CONFIG_64BIT
>>           pg |= PG_ELPA;
>>   #endif
>> +        if (cpu_has_rixiex)
>> +            pg |= PG_IEC;
>>           write_c0_pagegrain(pg);
>>       }
> David, I think it is still better to use set_c0_pagegrain() because
> PageGrain has a lot of RW bits now and clear all of them may be not good.

IMHO all the code that sets PageGrain should be in this function.  We 
should calculate all the bits here that should be set, and set them.

The whole reason that we have this mess, is that we were setting the 
bits at different code sites, and clobbering them in others.

If *all* the PageGrain logic is in one place, we won't have this problem.

If you think this patch is incorrect, then we should revert the other 
two and take our time to carefully do something that is correct.

David Daney