From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1on0113.outbound.protection.outlook.com [157.56.110.113]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id C0D3C1A0A2C for ; Thu, 8 Jan 2015 06:44:53 +1100 (AEDT) Message-ID: <54AD8C8A.8070100@Freescale.com> Date: Wed, 7 Jan 2015 13:44:10 -0600 From: Emil Medve MIME-Version: 1.0 To: Scott Wood , Xie Shaohui-B21989 Subject: Re: [PATCH] [v3] power/fsl: add MDIO dt binding for FMan References: <1419321466-5575-1-git-send-email-shh.xie@gmail.com> <1420590520.4961.38.camel@freescale.com> <1420653934.4961.58.camel@freescale.com> In-Reply-To: <1420653934.4961.58.camel@freescale.com> Content-Type: text/plain; charset="utf-8" Cc: "devicetree@vger.kernel.org" , "linuxppc-dev@lists.ozlabs.org" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hello Scott, On 01/07/2015 12:05 PM, Scott Wood wrote: > On Tue, 2015-01-06 at 23:29 -0600, Xie Shaohui-B21989 wrote: >>>>> +- interrupts >>>>> + Usage: optional >>>>> + Value type: >>>>> + Definition: Event interrupt of external MDIO controller. >>>>> + 1 Gb/s MDIO and 10 Gb/s MDIO has one interrupt respectively. >>> >>> I'm confused by "respectively" here. Does fsl,fman-memac-mdio have two >>> interrupts (one for 1 Gb/s and one for 10 Gb/s)? >> [S.H] We use two MDIO controllers for external PHY management. One for 1 Gb/s, >> One for 10 Gb/s, and two MDIO interrupts connected to MPIC. > > If there can be two interrupts you need to make that clear and specify > the order. > > Is it possible for one MDIO controller to have an interrupt connected > but not the other, on the same system? How would you represent that in > the device tree? If there are two MDIO controllers why are they in the > same node? Historically (FMan v2 and even before/legacy) we've had each MAC include an MDIO controller, but only one MDIO controller per MAC type/speed (1 Gb/s vs 10 Gb/s) is pinned out and all the same speed PHY(s) are connected to the respective MDIO controllers. As such the first 1 Gb/s MAC/MDIO controller is used to manage all the 1 Gb/s PHY(s) and the first 10 Gb/s MAC/MDIO controller is used to manage all the 10 Gb/s PHY(s). Each MDIO controller has the ability to generate interrupts but only pinned out MDIO controllers are hooked up to the MPIC (as such the talk about two interrupts) (Each MAC has also integrated a SERDES/TBI/"internal" PHY that is connected to the "local" MDIO controller) As you can imagine this creates a number of problems in a partitioning scenario (and not just, imagine RCWs where the first MAC is not used/enabled). In order to help a bit (but not quite enough), in FMan v3, two additional MDIO controllers (one for 1 the Gb/s PHY(s) and one for 1 the 10 Gb/s PHY(s)) have been integrated that are not associated with any MAC and these are the pinned out MDIO controllers on such SoC(s) (chassis v2) >> Does "optional" mean it's used if and >>> only if external MDIO is used, or is it optional even with external MDIO? I see >>> it's not present in the example -- do we not have a real example that has the >>> interrupt? >> [S.H] "optional" means it's available on hardware, but MDIO driver does not use interrupt. >> So we don't have a real example. > > The device tree describes the hardware, not the > driver Anyway, only two MDIO nodes (out of 4 to 14) would have an interrupt property describing exactly one interrupt. What language should we use to convey this situation Cheers, From mboxrd@z Thu Jan 1 00:00:00 1970 From: Emil Medve Subject: Re: [PATCH] [v3] power/fsl: add MDIO dt binding for FMan Date: Wed, 7 Jan 2015 13:44:10 -0600 Message-ID: <54AD8C8A.8070100@Freescale.com> References: <1419321466-5575-1-git-send-email-shh.xie@gmail.com> <1420590520.4961.38.camel@freescale.com> <1420653934.4961.58.camel@freescale.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1420653934.4961.58.camel@freescale.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+glppe-linuxppc-embedded-2=m.gmane.org@lists.ozlabs.org Sender: "Linuxppc-dev" To: Scott Wood , Xie Shaohui-B21989 Cc: "devicetree@vger.kernel.org" , "linuxppc-dev@lists.ozlabs.org" List-Id: devicetree@vger.kernel.org SGVsbG8gU2NvdHQsCgoKT24gMDEvMDcvMjAxNSAxMjowNSBQTSwgU2NvdHQgV29vZCB3cm90ZToK PiBPbiBUdWUsIDIwMTUtMDEtMDYgYXQgMjM6MjkgLTA2MDAsIFhpZSBTaGFvaHVpLUIyMTk4OSB3 cm90ZToKPj4+Pj4gKy0gaW50ZXJydXB0cwo+Pj4+PiArCQlVc2FnZTogb3B0aW9uYWwKPj4+Pj4g KwkJVmFsdWUgdHlwZTogPHByb3AtZW5jb2RlZC1hcnJheT4KPj4+Pj4gKwkJRGVmaW5pdGlvbjog RXZlbnQgaW50ZXJydXB0IG9mIGV4dGVybmFsIE1ESU8gY29udHJvbGxlci4KPj4+Pj4gKwkJMSBH Yi9zIE1ESU8gYW5kIDEwIEdiL3MgTURJTyBoYXMgb25lIGludGVycnVwdCByZXNwZWN0aXZlbHku Cj4+Pgo+Pj4gSSdtIGNvbmZ1c2VkIGJ5ICJyZXNwZWN0aXZlbHkiIGhlcmUuICBEb2VzIGZzbCxm bWFuLW1lbWFjLW1kaW8gaGF2ZSB0d28KPj4+IGludGVycnVwdHMgKG9uZSBmb3IgMSBHYi9zIGFu ZCBvbmUgZm9yIDEwIEdiL3MpPwo+PiBbUy5IXSBXZSB1c2UgdHdvIE1ESU8gY29udHJvbGxlcnMg Zm9yIGV4dGVybmFsIFBIWSBtYW5hZ2VtZW50LiBPbmUgZm9yIDEgR2IvcywKPj4gT25lIGZvciAx MCBHYi9zLCBhbmQgdHdvIE1ESU8gaW50ZXJydXB0cyBjb25uZWN0ZWQgdG8gTVBJQy4KPiAKPiBJ ZiB0aGVyZSBjYW4gYmUgdHdvIGludGVycnVwdHMgeW91IG5lZWQgdG8gbWFrZSB0aGF0IGNsZWFy IGFuZCBzcGVjaWZ5Cj4gdGhlIG9yZGVyLgo+IAo+IElzIGl0IHBvc3NpYmxlIGZvciBvbmUgTURJ TyBjb250cm9sbGVyIHRvIGhhdmUgYW4gaW50ZXJydXB0IGNvbm5lY3RlZAo+IGJ1dCBub3QgdGhl IG90aGVyLCBvbiB0aGUgc2FtZSBzeXN0ZW0/ICBIb3cgd291bGQgeW91IHJlcHJlc2VudCB0aGF0 IGluCj4gdGhlIGRldmljZSB0cmVlPyAgSWYgdGhlcmUgYXJlIHR3byBNRElPIGNvbnRyb2xsZXJz IHdoeSBhcmUgdGhleSBpbiB0aGUKPiBzYW1lIG5vZGU/CgpIaXN0b3JpY2FsbHkgKEZNYW4gdjIg YW5kIGV2ZW4gYmVmb3JlL2xlZ2FjeSkgd2UndmUgaGFkIGVhY2ggTUFDIGluY2x1ZGUKYW4gTURJ TyBjb250cm9sbGVyLCBidXQgb25seSBvbmUgTURJTyBjb250cm9sbGVyIHBlciBNQUMgdHlwZS9z cGVlZCAoMQpHYi9zIHZzIDEwIEdiL3MpIGlzIHBpbm5lZCBvdXQgYW5kIGFsbCB0aGUgc2FtZSBz cGVlZCBQSFkocykgYXJlCmNvbm5lY3RlZCB0byB0aGUgcmVzcGVjdGl2ZSBNRElPIGNvbnRyb2xs ZXJzLiBBcyBzdWNoIHRoZSBmaXJzdCAxIEdiL3MKTUFDL01ESU8gY29udHJvbGxlciBpcyB1c2Vk IHRvIG1hbmFnZSBhbGwgdGhlIDEgR2IvcyBQSFkocykgYW5kIHRoZQpmaXJzdCAxMCBHYi9zIE1B Qy9NRElPIGNvbnRyb2xsZXIgaXMgdXNlZCB0byBtYW5hZ2UgYWxsIHRoZSAxMCBHYi9zClBIWShz KS4gRWFjaCBNRElPIGNvbnRyb2xsZXIgaGFzIHRoZSBhYmlsaXR5IHRvIGdlbmVyYXRlIGludGVy cnVwdHMgYnV0Cm9ubHkgcGlubmVkIG91dCBNRElPIGNvbnRyb2xsZXJzIGFyZSBob29rZWQgdXAg dG8gdGhlIE1QSUMgKGFzIHN1Y2ggdGhlCnRhbGsgYWJvdXQgdHdvIGludGVycnVwdHMpCgooRWFj aCBNQUMgaGFzIGFsc28gaW50ZWdyYXRlZCBhIFNFUkRFUy9UQkkvImludGVybmFsIiBQSFkgdGhh dCBpcwpjb25uZWN0ZWQgdG8gdGhlICJsb2NhbCIgTURJTyBjb250cm9sbGVyKQoKQXMgeW91IGNh biBpbWFnaW5lIHRoaXMgY3JlYXRlcyBhIG51bWJlciBvZiBwcm9ibGVtcyBpbiBhIHBhcnRpdGlv bmluZwpzY2VuYXJpbyAoYW5kIG5vdCBqdXN0LCBpbWFnaW5lIFJDV3Mgd2hlcmUgdGhlIGZpcnN0 IE1BQyBpcyBub3QKdXNlZC9lbmFibGVkKS4gSW4gb3JkZXIgdG8gaGVscCBhIGJpdCAoYnV0IG5v dCBxdWl0ZSBlbm91Z2gpLCBpbiBGTWFuCnYzLCB0d28gYWRkaXRpb25hbCBNRElPIGNvbnRyb2xs ZXJzIChvbmUgZm9yIDEgdGhlIEdiL3MgUEhZKHMpIGFuZCBvbmUKZm9yIDEgdGhlIDEwIEdiL3Mg UEhZKHMpKSBoYXZlIGJlZW4gaW50ZWdyYXRlZCB0aGF0IGFyZSBub3QgYXNzb2NpYXRlZAp3aXRo IGFueSBNQUMgYW5kIHRoZXNlIGFyZSB0aGUgcGlubmVkIG91dCBNRElPIGNvbnRyb2xsZXJzIG9u IHN1Y2gKU29DKHMpIChjaGFzc2lzIHYyKQoKPj4gICBEb2VzICJvcHRpb25hbCIgbWVhbiBpdCdz IHVzZWQgaWYgYW5kCj4+PiBvbmx5IGlmIGV4dGVybmFsIE1ESU8gaXMgdXNlZCwgb3IgaXMgaXQg b3B0aW9uYWwgZXZlbiB3aXRoIGV4dGVybmFsIE1ESU8/ICBJIHNlZQo+Pj4gaXQncyBub3QgcHJl c2VudCBpbiB0aGUgZXhhbXBsZSAtLSBkbyB3ZSBub3QgaGF2ZSBhIHJlYWwgZXhhbXBsZSB0aGF0 IGhhcyB0aGUKPj4+IGludGVycnVwdD8KPj4gW1MuSF0gIm9wdGlvbmFsIiBtZWFucyBpdCdzIGF2 YWlsYWJsZSBvbiBoYXJkd2FyZSwgYnV0IE1ESU8gZHJpdmVyIGRvZXMgbm90IHVzZSBpbnRlcnJ1 cHQuIAo+PiBTbyB3ZSBkb24ndCBoYXZlIGEgcmVhbCBleGFtcGxlLgo+IAo+IDxyZWNvcmQgdHlw ZT0iYnJva2VuIj5UaGUgZGV2aWNlIHRyZWUgZGVzY3JpYmVzIHRoZSBoYXJkd2FyZSwgbm90IHRo ZQo+IGRyaXZlcjwvcmVjb3JkPgoKQW55d2F5LCBvbmx5IHR3byBNRElPIG5vZGVzIChvdXQgb2Yg NCB0byAxNCkgd291bGQgaGF2ZSBhbiBpbnRlcnJ1cHQKcHJvcGVydHkgZGVzY3JpYmluZyBleGFj dGx5IG9uZSBpbnRlcnJ1cHQuIFdoYXQgbGFuZ3VhZ2Ugc2hvdWxkIHdlIHVzZQp0byBjb252ZXkg dGhpcyBzaXR1YXRpb24KCgpDaGVlcnMsCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX18KTGludXhwcGMtZGV2IG1haWxpbmcgbGlzdApMaW51eHBwYy1kZXZA bGlzdHMub3psYWJzLm9yZwpodHRwczovL2xpc3RzLm96bGFicy5vcmcvbGlzdGluZm8vbGludXhw cGMtZGV2