From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH] Flush TLB when D bit is manually changed. Date: Fri, 09 Jan 2015 10:09:59 +0100 Message-ID: <54AF9AE7.4000503@redhat.com> References: <1420793070-27529-1-git-send-email-kai.huang@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit To: kvm@vger.kernel.org Return-path: Received: from plane.gmane.org ([80.91.229.3]:57681 "EHLO plane.gmane.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932145AbbAIJTN (ORCPT ); Fri, 9 Jan 2015 04:19:13 -0500 Received: from list by plane.gmane.org with local (Exim 4.69) (envelope-from ) id 1Y9Vf1-0007m9-M4 for kvm@vger.kernel.org; Fri, 09 Jan 2015 10:15:15 +0100 Received: from net-37-117-147-67.cust.vodafonedsl.it ([37.117.147.67]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Fri, 09 Jan 2015 10:15:15 +0100 Received: from pbonzini by net-37-117-147-67.cust.vodafonedsl.it with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Fri, 09 Jan 2015 10:15:15 +0100 In-Reply-To: <1420793070-27529-1-git-send-email-kai.huang@linux.intel.com> Sender: kvm-owner@vger.kernel.org List-ID: On 09/01/2015 09:44, Kai Huang wrote: > When software changes D bit (either from 1 to 0, or 0 to 1), the corresponding > TLB entity in the hardware won't be updated immediately. We should flush it to > guarantee the consistence of D bit between TLB and MMU page table in memory. > This is required if some specific hardware feature uses D-bit status to do > specific things. > > Sanity test was done on my machine with Intel processor. > > Signed-off-by: Kai Huang > --- > arch/x86/kvm/mmu.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c > index 978f402..1feac0c 100644 > --- a/arch/x86/kvm/mmu.c > +++ b/arch/x86/kvm/mmu.c > @@ -547,6 +547,11 @@ static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) > return (old_spte & bit_mask) && !(new_spte & bit_mask); > } > > +static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask) > +{ > + return (old_spte & bit_mask) != (new_spte & bit_mask); > +} > + > /* Rules for using mmu_spte_set: > * Set the sptep from nonpresent to present. > * Note: the sptep being assigned *must* be either not present > @@ -597,6 +602,13 @@ static bool mmu_spte_update(u64 *sptep, u64 new_spte) > if (!shadow_accessed_mask) > return ret; > > + /* > + * We also need to flush TLB when D-bit is changed by software to > + * guarantee the D-bit consistence between TLB and MMU page table. > + */ > + if (spte_is_bit_changed(old_spte, new_spte, shadow_dirty_mask)) I think shadow_accessed_mask needs to be checked too. I made the change and applied the patch. Paolo > + ret = true; > + > if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) > kvm_set_pfn_accessed(spte_to_pfn(old_spte)); > if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) >