From mboxrd@z Thu Jan 1 00:00:00 1970 From: Xiao Guangrong Subject: Re: [PATCH] Flush TLB when D bit is manually changed. Date: Fri, 09 Jan 2015 17:50:43 +0800 Message-ID: <54AFA473.8080003@linux.intel.com> References: <1420793070-27529-1-git-send-email-kai.huang@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit To: Kai Huang , pbonzini@redhat.com, kvm@vger.kernel.org Return-path: Received: from mga09.intel.com ([134.134.136.24]:50637 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755182AbbAIJvY (ORCPT ); Fri, 9 Jan 2015 04:51:24 -0500 In-Reply-To: <1420793070-27529-1-git-send-email-kai.huang@linux.intel.com> Sender: kvm-owner@vger.kernel.org List-ID: On 01/09/2015 04:44 PM, Kai Huang wrote: > When software changes D bit (either from 1 to 0, or 0 to 1), the corresponding > TLB entity in the hardware won't be updated immediately. We should flush it to > guarantee the consistence of D bit between TLB and MMU page table in memory. > This is required if some specific hardware feature uses D-bit status to do > specific things. > Currently, A/D is lazied synced and it does not hurt anything since we have marked the page dirty after clearing the bit and mmu-notifier can keep the coherence on host (It is the guest's responsibility to sync TLBs when changing the bit). So, i am just curious what "some specific hardware" is. :)