From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:41963)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <Claudio.Fontana@huawei.com>) id 1YAxTh-0002iR-GK
	for qemu-devel@nongnu.org; Tue, 13 Jan 2015 04:09:34 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <Claudio.Fontana@huawei.com>) id 1YAxTc-000718-I7
	for qemu-devel@nongnu.org; Tue, 13 Jan 2015 04:09:33 -0500
Received: from lhrrgout.huawei.com ([194.213.3.17]:46802)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <Claudio.Fontana@huawei.com>) id 1YAxTc-000712-AK
	for qemu-devel@nongnu.org; Tue, 13 Jan 2015 04:09:28 -0500
Message-ID: <54B4E0B4.4010201@huawei.com>
Date: Tue, 13 Jan 2015 10:09:08 +0100
From: Claudio Fontana <claudio.fontana@huawei.com>
MIME-Version: 1.0
References: <1420560191-48029-1-git-send-email-agraf@suse.de>
	<1420560191-48029-3-git-send-email-agraf@suse.de>
	<CAH47eN2KJOeVbPjJdX0OOGhYo5PSr-Typ0yf=hmJ5XXqQo1hWg@mail.gmail.com>
	<54B40692.9040909@suse.de>
	<CAFEAcA-RGoJtrBKCQK+NmVfXo+bu2JFBCZG-XdroW08DHsY_7Q@mail.gmail.com>
	<54B4375E.3070200@suse.de>
	<CAFEAcA8xQSj+jCX7UJYLTWajJ2x1gTNL492G9nOuP7=GSBaryw@mail.gmail.com>
In-Reply-To: <CAFEAcA8xQSj+jCX7UJYLTWajJ2x1gTNL492G9nOuP7=GSBaryw@mail.gmail.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH 2/4] pci: Add generic PCIe host bridge
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Maydell <peter.maydell@linaro.org>, Alexander Graf <agraf@suse.de>
Cc: Rob Herring <rob.herring@linaro.org>, Ard Biesheuvel <ard.biesheuvel@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>, "Michael S. Tsirkin" <mst@redhat.com>, "stuart.yoder@freescale.com" <stuart.yoder@freescale.com>, alvise rigo <a.rigo@virtualopensystems.com>

On 12.01.2015 22:20, Peter Maydell wrote:
> On 12 January 2015 at 21:06, Alexander Graf <agraf@suse.de> wrote:
>>
>>
>> On 12.01.15 21:08, Peter Maydell wrote:
>>> On 12 January 2015 at 17:38, Alexander Graf <agraf@suse.de> wrote:
>>>> I'd prefer to keep things as easy as we humanly can for now. Then add
>>>> MSI. And if we then realize that we still need 4 rather than 1 shared
>>>> interrupt lines we can still change it :)
>>>
>>> Except that that would be a breaking change, so I would prefer
>>> to think ahead where possible; at some point there will come
>>> a time when we really can't make breaking changes to this
>>> board any more...
>>
>> Works for me, then we stay at a single interrupt line. The only reason
>> we have 4 in PCI is that back in the day you could have non-sharing PCI
>> devices that were essentially ISA ones.
> 
> Well, also your typical small system probably doesn't have more
> than 4 PCI slots and so 4 IRQs is enough to give them each one.
> Most small VMs probably won't have more than four PCI devices
> either...
> 
> -- PMM
> 

This solution with 4 slots, 4 irqs would be preferable to me..

Ciao,

Claudio