From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH for-4.6 3/4] xen/arm: vgic: notice if the vIRQ is not allocated when the guest enable it Date: Thu, 15 Jan 2015 13:27:09 +0000 Message-ID: <54B7C02D.9060300@linaro.org> References: <1418395392-30460-1-git-send-email-julien.grall@linaro.org> <1418395392-30460-4-git-send-email-julien.grall@linaro.org> <1421164500.19103.132.camel@citrix.com> <54B5810E.2030203@linaro.org> <1421238505.19103.250.camel@citrix.com> <54B66421.4030803@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YBkSa-0002eO-5d for xen-devel@lists.xenproject.org; Thu, 15 Jan 2015 13:27:40 +0000 Received: by mail-wg0-f50.google.com with SMTP id a1so14887131wgh.9 for ; Thu, 15 Jan 2015 05:27:38 -0800 (PST) In-Reply-To: <54B66421.4030803@linaro.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: xen-devel@lists.xenproject.org, stefano.stabellini@citrix.com, tim@xen.org, parth.dixit@linaro.org, christoffer.dall@linaro.org List-Id: xen-devel@lists.xenproject.org Hi Ian, On 14/01/15 12:42, Julien Grall wrote: > On 14/01/15 12:28, Ian Campbell wrote: >> On Tue, 2015-01-13 at 20:33 +0000, Julien Grall wrote: >>> On 13/01/15 15:55, Ian Campbell wrote: >>>> On Fri, 2014-12-12 at 14:43 +0000, Julien Grall wrote: >>>>> This help for guest interrupts debugging. If the vIRQ is not allocate, >>>>> this means that nothing is wired to it. >>>> >>>> Should we short circuit the rest of the enable operation for this IRQ >>>> then? i.e. implement such writes as ignored, e.g. not reflect it in >>>> reads of ISENABLER etc. >>>> >>>> What (if anything) does the GIC spec have to say on the subject? >>> >>> "A register bit corresponding to an unimplemented interrupt is RAZ/WI." >>> >>> The goal of this print was mostly for debugging physical IRQ routed to a >>> guest. >>> >>> I could extend to ignore write to any register that should be RAZ/WI for >>> this specific interrupt. >> >> Since those are the defined semantics I think that is the best thing to >> do. > > Ok. I will look at it to see how we can implement it. So I looked to the code. It may need some rework to effectively implement most of registers bits RAZ/WI when the interrupt doesn't exist. As this series is required for the ACPI series, I suggest to defer this work in a follow-up series. Regards, -- Julien Grall