From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>,
Greg Bellows <greg.bellows@linaro.org>
Cc: Sergey Fedorov <serge.fdrv@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Fabian Aggeler <aggelerf@ethz.ch>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v7 05/32] target-arm: make arm_current_el() return EL3
Date: Mon, 19 Jan 2015 09:44:10 -0800 [thread overview]
Message-ID: <54BD426A.5070107@twiddle.net> (raw)
In-Reply-To: <CAFEAcA-c1OXi-DreK2wzi8mhRT_RTYkGPDGy7pJpoTya=RQnUA@mail.gmail.com>
On 01/19/2015 05:22 AM, Peter Maydell wrote:
> Richard: do you have a feel for how expensive it is to
> have lots and lots of mmu modes? I might be able to
> merge "S EL1" with "NS EL1 stage 1+2" and ditto "S EL0"
> with "NS EL0 stage1 + 2" but we'd need to do more TLB
> flushing and it's not clear to me currently exactly
> where the extra flushes would have to go...
It's 10k per mmu mode, more or less. That's what you've
got to memset (to -1) whenever a flush occurs.
With the obvious mathematics wrt flush rate that implies.
r~
next prev parent reply other threads:[~2015-01-19 17:44 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-21 16:55 [Qemu-devel] [PATCH v7 00/32] target-arm: add Security Extensions for CPUs Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 01/32] target-arm: increase arrays of registers R13 & R14 Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 02/32] target-arm: add arm_is_secure() function Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 03/32] target-arm: reject switching to monitor mode Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 04/32] target-arm: rename arm_current_pl to arm_current_el Greg Bellows
2014-10-23 14:53 ` Peter Maydell
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 05/32] target-arm: make arm_current_el() return EL3 Greg Bellows
2015-01-16 18:36 ` Peter Maydell
2015-01-19 13:22 ` Peter Maydell
2015-01-19 17:44 ` Richard Henderson [this message]
2015-01-19 19:00 ` Peter Maydell
2015-01-19 19:30 ` Richard Henderson
2015-01-19 22:54 ` Edgar E. Iglesias
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 06/32] target-arm: A32: Emulate the SMC instruction Greg Bellows
2014-10-23 14:06 ` Peter Maydell
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 07/32] target-arm: extend async excp masking Greg Bellows
2014-10-24 16:25 ` Peter Maydell
2014-10-24 22:43 ` Greg Bellows
2014-10-26 22:30 ` Peter Maydell
2014-10-27 11:57 ` Peter Maydell
2014-10-27 15:59 ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 08/32] target-arm: add async excp target_el function Greg Bellows
2014-10-24 16:26 ` Peter Maydell
2014-10-28 14:50 ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 09/32] target-arm: add banked register accessors Greg Bellows
2014-10-24 16:37 ` Peter Maydell
2014-10-28 18:42 ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 10/32] target-arm: add non-secure Translation Block flag Greg Bellows
2014-10-24 16:40 ` Peter Maydell
2014-10-28 15:21 ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 11/32] target-arm: add CPREG secure state support Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 12/32] target-arm: add secure state bit to CPREG hash Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 13/32] target-arm: insert AArch32 cpregs twice into hashtable Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 14/32] target-arm: move AArch32 SCR into security reglist Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 17/32] target-arm: add NSACR register Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 18/32] target-arm: add SDER definition Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 19/32] target-arm: add MVBAR support Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 20/32] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 21/32] target-arm: make CSSELR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 22/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 23/32] target-arm: add TCR_EL3 and make TTBCR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 24/32] target-arm: make c2_mask and c2_base_mask banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 25/32] target-arm: make DACR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 26/32] target-arm: make IFSR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 27/32] target-arm: make DFSR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 28/32] target-arm: make IFAR/DFAR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 29/32] target-arm: make PAR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 31/32] target-arm: make MAIR0/1 banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows
2014-10-23 14:19 ` [Qemu-devel] [PATCH v7 00/32] target-arm: add Security Extensions for CPUs Peter Maydell
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