From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH 05/10] xen/arm: vgic-v3: Document the current restrictions Date: Wed, 21 Jan 2015 13:19:47 +0000 Message-ID: <54BFA773.2010904@linaro.org> References: <1421684957-29884-1-git-send-email-julien.grall@linaro.org> <1421684957-29884-6-git-send-email-julien.grall@linaro.org> <1421769643.10440.309.camel@citrix.com> <54BE952E.6040304@linaro.org> <1421842611.13271.20.camel@citrix.com> <54BF9CA7.7000008@linaro.org> <1421844486.13271.38.camel@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YDvCk-0004Rw-5s for xen-devel@lists.xenproject.org; Wed, 21 Jan 2015 13:20:18 +0000 Received: by mail-wi0-f169.google.com with SMTP id bs8so33377779wib.0 for ; Wed, 21 Jan 2015 05:20:16 -0800 (PST) In-Reply-To: <1421844486.13271.38.camel@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: xen-devel@lists.xenproject.org, tim@xen.org, stefano.stabellini@citrix.com List-Id: xen-devel@lists.xenproject.org On 21/01/15 12:48, Ian Campbell wrote: > On Wed, 2015-01-21 at 12:33 +0000, Julien Grall wrote: >> On 21/01/15 12:16, Ian Campbell wrote: >>> On Tue, 2015-01-20 at 17:49 +0000, Julien Grall wrote: >>> >>>>>> - A processor can only access his own redistributor. For buggy >>>>>> assumption, the current code bank the redistributors MMIO. >>>>> >>>>> What assumption? It's not clear if you mean that a foreign redistributor >>>>> should not be accessible and is, or if it should be accessible and >>>>> isn't. >>>> >>>> Every redistributor (one per processor) are mapped in distinct MMIO region. >>>> >>>> Unlike the distributor, the redistributor is not banked. >>> >>> Understood. >>> >>>> Our current implementation (see vgic_v3_rdistr_mmio_write) consider that >>>> the redistributor is banked and replicate n-times in the memory. >>> >>> IOW instead of having e.g. 8 individual redistributors each vcpu sees >>> it's own redistributor 8 times. That does seem a bit dubious. >> >> It's the current behavior. You can see the difference in linux log. The >> address of each redistributor is the same. > > Are you sure that isn't the "redistributor region"? One of those can > contain multiple redistributors, i.e. gic_v3_init sets up a single > region and that propagates to the DTB given to the guest. > > So the error is just in the mmio decode stage I think, not in the setup > we are trying to achieve. Right, the device tree is valid, we expose a region containing enough space for up to 8 distributor. The problem is in our MMIO emulation. >>>> If you give a look to the redistributor iniatialization (see Xen and >>>> Linux GICv3 code). The code will go through all the redistributors and >>>> check GICR_TYPER to see if the processor is associated to this >>>> redistributor. >>>> >>>> I'm not sure how the redistributor should behave if it's accessed by >>>> another processor. >>> >>> Please can you find a spec reference and include it in the clarified >>> version of this item. >> >> Rather than the distributor, there is multiple redistributor (one per >> processor). >> >> I think the section 5.4.1 in the GICv3 should answer to this question: >> >> "Each re-distributor must be allocated at one page for controlling the >> overall behavior of the re-distributor and for controlling physical >> LPIs. The base address of this page is referred to as RD_base. In >> addition, each re-distributor must be also allocated the following >> additional pages". > > That doesn't say anything about one CPU touching another's > redistributor. Linux is at least using GICR_TYPER, to retrieve the right distributor. For the other the register I've no idea. I've asked ARM. Let see what they will answer. -- Julien Grall