Re: Hardware breakpoints on MIPS

[David Daney <ddaney.cavm@gmail.com>]

On 01/29/2015 03:43 PM, Bruce Korb wrote:
> Thank you!
>
> On Thu, Jan 29, 2015 at 3:01 PM, David Daney <ddaney.cavm@gmail.com> wrote:
>>> Anyway, I need to set a hardware breakpoint on a Mips CPU on a "Cavium"
>>> platform
>>> in a kernel module.
>>
>> This would appear to be for the most part, completely independent of GDB,
>
> I had guessed as much, but did not have a better guess, either.
>
>> Since many years ago, WatchLo and WatchHi have been under the control of the
>> Linux kernel.  If you set these registers and a Watch Exception is
>> triggered, it will cause the registers to be cleared and the exception will
>> be ignored, unless they were configured via ptrace(2) for userspace
>> addresses.
>
> Can a hacked ptrace set it up to panic instead?
> All I need is a stack trace once this one single spot in memory gets written.
>

Look at do_watch() in traps.c, you would have to doctor that function up 
to generate the stacktrace.

>> For debugging kernel space with watchpoint registers on OCTEON it is
>> probably best to use the facilities in the EJTAG unit.
>
> Which, I'll hazard a guess, requires physical access.
> I'll have to go begging and pleading for special access to the Hardware Lab.
> Please don't ask me why we software types are kept out.
> I've not gotten a straight answer, so I could only answer with speculation.
>
>
> *sigh*.  Thank you.
>
>