From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v2 04/15] xen/arm: vgic-v3: Correctly handle RAZ/WI registers Date: Mon, 02 Feb 2015 15:59:49 +0000 Message-ID: <54CF9EF5.6080804@linaro.org> References: <1422555950-31821-1-git-send-email-julien.grall@linaro.org> <1422555950-31821-5-git-send-email-julien.grall@linaro.org> <1422890663.4801.20.camel@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YIJQG-0002bW-DG for xen-devel@lists.xenproject.org; Mon, 02 Feb 2015 16:00:24 +0000 Received: by mail-we0-f179.google.com with SMTP id q59so39890362wes.10 for ; Mon, 02 Feb 2015 08:00:23 -0800 (PST) In-Reply-To: <1422890663.4801.20.camel@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: xen-devel@lists.xenproject.org, Vijaya.Kumar@caviumnetworks.com, stefano.stabellini@citrix.com, tim@xen.org List-Id: xen-devel@lists.xenproject.org Hi Ian, On 02/02/15 15:24, Ian Campbell wrote: > On Thu, 2015-01-29 at 18:25 +0000, Julien Grall wrote: >> Some of the registers are accessible via multiple size (see GICD_IPRIORITYR*). >> >> Thoses registers are misimplemented when they should be RAZ. Only > > "Those" and "incorrectly implemented". > >> word-access size are currently allowed for them. >> >> To avoid further issues, introduce different label following the access-size >> of the registers: >> - read_as_zero_64 and write_ignore_64: Used for registers accessible >> via a double-word. >> - read_as_zero_32 and write_ignore_32: Used for registers accessible >> via a word. > > 5.1.3 suggests there are at least some 64-bit registers where it ought > to be possible to read the upper and lower halves independently. Don't > you need to support that? Only when the system is supporting AArch32. If the system only supports AArch64, 64-bit registers can only be read via a 64-bit access. I don't think we actually support AArch32 on the vGICv3 drivers. And we don't emulate 32-bits access on 64-bit registers. I will give a look to it. > BTW, a reference to 5.1.3 in the changelog would be handy. I will also mention the version of the document as this paragraph doesn't exists on the previous version. Regards, -- Julien Grall