From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@linaro.org>
Subject: Re: [PATCH v2 11/15] xen/arm: vgic-v2: Correctly handle
	RAZ/WI registers
Date: Mon, 02 Feb 2015 17:08:29 +0000
Message-ID: <54CFAF0D.7090403@linaro.org>
References: <1422555950-31821-1-git-send-email-julien.grall@linaro.org>		
	<1422555950-31821-12-git-send-email-julien.grall@linaro.org>	
	<1422892959.5838.23.camel@citrix.com> <54CFA774.3010904@linaro.org>
	<1422895851.5838.34.camel@citrix.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <xen-devel-bounces@lists.xen.org>
Received: from mail6.bemta4.messagelabs.com ([85.158.143.247])
	by lists.xen.org with esmtp (Exim 4.72)
	(envelope-from <julien.grall@linaro.org>) id 1YIKUc-00031R-Qq
	for xen-devel@lists.xenproject.org; Mon, 02 Feb 2015 17:08:58 +0000
Received: by mail-wi0-f182.google.com with SMTP id n3so16458991wiv.3
	for <xen-devel@lists.xenproject.org>;
	Mon, 02 Feb 2015 09:08:57 -0800 (PST)
In-Reply-To: <1422895851.5838.34.camel@citrix.com>
List-Unsubscribe: <http://lists.xen.org/cgi-bin/mailman/options/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=unsubscribe>
List-Post: <mailto:xen-devel@lists.xen.org>
List-Help: <mailto:xen-devel-request@lists.xen.org?subject=help>
List-Subscribe: <http://lists.xen.org/cgi-bin/mailman/listinfo/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=subscribe>
Sender: xen-devel-bounces@lists.xen.org
Errors-To: xen-devel-bounces@lists.xen.org
To: Ian Campbell <Ian.Campbell@citrix.com>
Cc: xen-devel@lists.xenproject.org, Vijaya.Kumar@caviumnetworks.com, tim@xen.org, stefano.stabellini@citrix.com
List-Id: xen-devel@lists.xenproject.org

On 02/02/15 16:50, Ian Campbell wrote:
> On Mon, 2015-02-02 at 16:36 +0000, Julien Grall wrote:
>> Hi Ian,
>>
>> On 02/02/15 16:02, Ian Campbell wrote:
>>> On Thu, 2015-01-29 at 18:25 +0000, Julien Grall wrote:
>>>> Some of the registers are accessible via multiple size (see GICD_IPRIORITYR*).
>>>
>>> They are byte accessible, but are they half word accessible? I suspect
>>> not.
>>
>> Only byte accessible.
> 
> I think we might need a read_as_zero_8_32 then, i.e. explicitly list the
> sizes which are allowed, and perhaps omit the un-suffixed version for so
> it's clear exactly what is what, although that might be more churn than
> you want to have here.

Hmmm, why? I was talking for registers defined in the spec. We don't
know if reserved/implementation defined registers will allow half-word
access.

The un-suffixed version is there when we don't need to check the size
because it has already been done. It seems pointless to check it again.

Regards,

-- 
Julien Grall