diff for duplicates of <54D00D0A.6050107@codeaurora.org>

diff --git a/a/1.txt b/N1/1.txt
index bca1e61..ac03c7e 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -77,9 +77,3 @@ On 02/02/2015 03:25 PM, Florian Fainelli wrote:
 > your PCIe device BARs are mapped from the CPU perspective, but you
 > definitively cannot rely on such assumptions, as there will be bogus HW
 > there, for which only a subsequent ioread32() will work.
-
-
-_______________________________________________
-ath10k mailing list
-ath10k@lists.infradead.org
-http://lists.infradead.org/mailman/listinfo/ath10k
diff --git a/a/content_digest b/N1/content_digest
index 91bb9f8..489f6cf 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -19,10 +19,10 @@
  "Date\0Mon, 02 Feb 2015 15:49:30 -0800\0"
  "To\0Florian Fainelli <f.fainelli@gmail.com>"
  " Johannes Berg <johannes@sipsolutions.net>\0"
- "Cc\0linux-wireless@vger.kernel.org"
-  Bob Copeland <me@bobcopeland.com>
-  Peter Oh <poh@qca.qualcomm.com>
- " ath10k@lists.infradead.org\0"
+ "Cc\0Bob Copeland <me@bobcopeland.com>"
+  linux-wireless@vger.kernel.org
+  ath10k@lists.infradead.org
+ " Peter Oh <poh@qca.qualcomm.com>\0"
  "\00:1\0"
  "b\0"
  "Hi Florian,\n"
@@ -103,12 +103,6 @@
  "> ARM synchronization barriers are propagated to the memory region where\n"
  "> your PCIe device BARs are mapped from the CPU perspective, but you\n"
  "> definitively cannot rely on such assumptions, as there will be bogus HW\n"
- "> there, for which only a subsequent ioread32() will work.\n"
- "\n"
- "\n"
- "_______________________________________________\n"
- "ath10k mailing list\n"
- "ath10k@lists.infradead.org\n"
- http://lists.infradead.org/mailman/listinfo/ath10k
+ > there, for which only a subsequent ioread32() will work.
 
-dffdffef70f4df7c4338dc990d61c15be35c0f91a5ca9285f1367a7e2e5405c8
+d54815ff2d2721a0cf7a1a23d0d6f59d93d901994a52973f335869861346c139
