From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v2 04/15] xen/arm: vgic-v3: Correctly handle RAZ/WI registers Date: Tue, 03 Feb 2015 13:37:00 +0000 Message-ID: <54D0CEFC.7060206@linaro.org> References: <1422555950-31821-1-git-send-email-julien.grall@linaro.org> <1422555950-31821-5-git-send-email-julien.grall@linaro.org> <1422890663.4801.20.camel@citrix.com> <54CF9EF5.6080804@linaro.org> <1422893292.5838.27.camel@citrix.com> <54CFA1B9.80405@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YIdfW-0008LC-6d for xen-devel@lists.xenproject.org; Tue, 03 Feb 2015 13:37:31 +0000 Received: by mail-wg0-f42.google.com with SMTP id x13so44750092wgg.1 for ; Tue, 03 Feb 2015 05:37:28 -0800 (PST) In-Reply-To: <54CFA1B9.80405@linaro.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: xen-devel@lists.xenproject.org, Vijaya.Kumar@caviumnetworks.com, stefano.stabellini@citrix.com, tim@xen.org List-Id: xen-devel@lists.xenproject.org On 02/02/15 16:11, Julien Grall wrote: > On 02/02/15 16:08, Ian Campbell wrote: >> On Mon, 2015-02-02 at 15:59 +0000, Julien Grall wrote: >>> Hi Ian, >>> >>> On 02/02/15 15:24, Ian Campbell wrote: >>>> On Thu, 2015-01-29 at 18:25 +0000, Julien Grall wrote: >>>>> Some of the registers are accessible via multiple size (see GICD_IPRIORITYR*). >>>>> >>>>> Thoses registers are misimplemented when they should be RAZ. Only >>>> >>>> "Those" and "incorrectly implemented". >>>> >>>>> word-access size are currently allowed for them. >>>>> >>>>> To avoid further issues, introduce different label following the access-size >>>>> of the registers: >>>>> - read_as_zero_64 and write_ignore_64: Used for registers accessible >>>>> via a double-word. >>>>> - read_as_zero_32 and write_ignore_32: Used for registers accessible >>>>> via a word. >>>> >>>> 5.1.3 suggests there are at least some 64-bit registers where it ought >>>> to be possible to read the upper and lower halves independently. Don't >>>> you need to support that? >>> >>> Only when the system is supporting AArch32. If the system only supports >>> AArch64, 64-bit registers can only be read via a 64-bit access. >>> >>> I don't think we actually support AArch32 on the vGICv3 drivers. And we >>> don't emulate 32-bits access on 64-bit registers. >> >> It's certainly our intention in general to support arm32 guest kernels >> on arm64, the v3 vgic may not reach that aspiration though. > > AFAICT, only the vGIC v3 is using 64-bit access. So we are fine for now. > > Linux seems to allow to build GICv3 for ARM32. I guess we should support > it in the future. So I was wrong, it's not possible to select GICv3 manually on ARM32. So I will update the commit message that we only support Aarch64 for now, therefore only 64-bit access is allowed. Supporting Aarch32 would require more work, so it's defer until someone care about this use case. Is it ok for you? Regards, -- Julien Grall