From: Ben Greear <greearb@candelatech.com>
To: Michal Kazior <michal.kazior@tieto.com>
Cc: ath10k <ath10k@lists.infradead.org>
Subject: Re: Unable to read firmware registers on crash?
Date: Tue, 03 Feb 2015 20:28:29 -0800 [thread overview]
Message-ID: <54D19FED.90102@candelatech.com> (raw)
In-Reply-To: <54D195C3.7060703@candelatech.com>
Well, it seems to work at least when I crash it nicely with the
debugfs firmware-assert hooks. Tested on x86...if I have endian
issues, things might go poorly on other platforms.
Here is patch I am using in ath10k... I added similar logic to the
CT firmware. Now, will have to see if we can reproduce the crash where
CE transport totally fails...
http://dmz2.candelatech.com/git/gitweb.cgi?p=linux-3.17.dev.y/.git;a=commitdiff;h=52333b889f0c818d2766d0d514ac31e5c53ce0ab;hp=997d36105fe9803bf7be0bbb6dba61710c3e8232
Comments welcome on the patch, though it has little to no chance of ever
making it upstream...
Thanks,
Ben
On 02/03/2015 07:45 PM, Ben Greear wrote:
> On 02/03/2015 06:26 AM, Michal Kazior wrote:
>> On 3 February 2015 at 14:57, Ben Greear <greearb@candelatech.com> wrote:
>
>>> That sounds reasonable. Do you know of any example code that accesses
>>> a target register or two with the MMIO logic on the host? I think firmware
>>> has some examples of how
>>> to fiddle with registers, so I think I can make a stab at that part....
>>
>> From what I understand the MMIO space is shared between host and
>> target program so there's no need for any special handling. You can
>> look for FW_IND_EVENT_PENDING and FW_INDICATOR_ADDRESS usage both in
>> firmware and ath10k - it's already used to notify host about a crash.
>> It should be pretty straightforward. The indicator address itself
>> seems to be a scratch register already and there are a few more so you
>> should be able to design a ping-pong protocol to pass data.
>
> While implementing this, I ran into a question:
>
> From what I can tell, the ath10k_pci_read32 and ath10k_pci_write32
> are treated like they return and write data in host-byte-order.
>
> But, iowrite32 and ioread32 are defined to be pci-byte-order which
> is little-endian?
> http://comments.gmane.org/gmane.linux.kernel/1042371
> (or is that bad info?)
>
> Do we need to be converting values to little-endian before
> writing them?
>
> And upon, read, do we need to convert them to host order?
>
> I guess we must not since it seems things mostly work now, but I
> am not sure why that is...
>
> Thanks,
> Ben
>
>
>
>>
>>
>> Michał
>>
>
>
--
Ben Greear <greearb@candelatech.com>
Candela Technologies Inc http://www.candelatech.com
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next prev parent reply other threads:[~2015-02-04 4:27 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-01 17:46 Unable to read firmware registers on crash? Ben Greear
2015-02-02 12:11 ` Michal Kazior
2015-02-02 17:03 ` Ben Greear
2015-02-03 6:31 ` Michal Kazior
2015-02-03 13:57 ` Ben Greear
2015-02-03 14:26 ` Michal Kazior
2015-02-04 3:45 ` Ben Greear
2015-02-04 4:28 ` Ben Greear [this message]
2015-02-06 12:19 ` Michal Kazior
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