[U-Boot] [PATCH V2 01/13] lcd: move platform-specific structs to their own headers

[Bo Shen <voice.shen@atmel.com>]

On 02/03/2015 07:32 PM, Nikita Kiryanov wrote:
> common/lcd code is full of platform-specific code and definitions, which
> ideally should reside with the respective driver code. Take a step towards that
> goal by moving platform-specific structs from lcd.h to their own header files.
>
> The structs for the generic case (the #else for all the platform-specific
> cases) is retained in lcd.h as the default case.
>
> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Cc: Bo Shen <voice.shen@atmel.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Anatolij Gustschin <agust@denx.de>

For Atmel part, tested ok on at91sam9g35ek.

Tested-by: Bo Shen <voice.shen@atmel.com>

> ---
> Changes in V2:
> 	- Minor commit message update
>
>   include/atmel_lcd.h  |  38 ++++++++++
>   include/exynos_lcd.h |  81 +++++++++++++++++++++
>   include/lcd.h        | 201 ++-------------------------------------------------
>   include/mpc823_lcd.h |  43 +++++++++++
>   include/pxa_lcd.h    |  80 ++++++++++++++++++++
>   5 files changed, 247 insertions(+), 196 deletions(-)
>   create mode 100644 include/atmel_lcd.h
>   create mode 100644 include/exynos_lcd.h
>   create mode 100644 include/mpc823_lcd.h
>   create mode 100644 include/pxa_lcd.h
>
> diff --git a/include/atmel_lcd.h b/include/atmel_lcd.h
> new file mode 100644
> index 0000000..fa8aa29
> --- /dev/null
> +++ b/include/atmel_lcd.h
> @@ -0,0 +1,38 @@
> +/*
> + * atmel_lcd.h - Atmel LCD Controller structures
> + *
> + * (C) Copyright 2001
> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef _ATMEL_LCD_H_
> +#define _ATMEL_LCD_H_
> +
> +typedef struct vidinfo {
> +	ushort vl_col;		/* Number of columns (i.e. 640) */
> +	ushort vl_row;		/* Number of rows (i.e. 480) */
> +	u_long vl_clk;	/* pixel clock in ps    */
> +
> +	/* LCD configuration register */
> +	u_long vl_sync;		/* Horizontal / vertical sync */
> +	u_long vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
> +	u_long vl_tft;		/* 0 = passive, 1 = TFT */
> +	u_long vl_cont_pol_low;	/* contrast polarity is low */
> +	u_long vl_clk_pol;	/* clock polarity */
> +
> +	/* Horizontal control register. */
> +	u_long vl_hsync_len;	/* Length of horizontal sync */
> +	u_long vl_left_margin;	/* Time from sync to picture */
> +	u_long vl_right_margin;	/* Time from picture to sync */
> +
> +	/* Vertical control register. */
> +	u_long vl_vsync_len;	/* Length of vertical sync */
> +	u_long vl_upper_margin;	/* Time from sync to picture */
> +	u_long vl_lower_margin;	/* Time from picture to sync */
> +
> +	u_long	mmio;		/* Memory mapped registers */
> +} vidinfo_t;
> +
> +#endif
> diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h
> new file mode 100644
> index 0000000..cf389da
> --- /dev/null
> +++ b/include/exynos_lcd.h
> @@ -0,0 +1,81 @@
> +/*
> + * exynos_lcd.h - Exynos LCD Controller structures
> + *
> + * (C) Copyright 2001
> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef _EXYNOS_LCD_H_
> +#define _EXYNOS_LCD_H_
> +
> +enum {
> +	FIMD_RGB_INTERFACE = 1,
> +	FIMD_CPU_INTERFACE = 2,
> +};
> +
> +enum exynos_fb_rgb_mode_t {
> +	MODE_RGB_P = 0,
> +	MODE_BGR_P = 1,
> +	MODE_RGB_S = 2,
> +	MODE_BGR_S = 3,
> +};
> +
> +typedef struct vidinfo {
> +	ushort vl_col;		/* Number of columns (i.e. 640) */
> +	ushort vl_row;		/* Number of rows (i.e. 480) */
> +	ushort vl_width;	/* Width of display area in millimeters */
> +	ushort vl_height;	/* Height of display area in millimeters */
> +
> +	/* LCD configuration register */
> +	u_char vl_freq;		/* Frequency */
> +	u_char vl_clkp;		/* Clock polarity */
> +	u_char vl_oep;		/* Output Enable polarity */
> +	u_char vl_hsp;		/* Horizontal Sync polarity */
> +	u_char vl_vsp;		/* Vertical Sync polarity */
> +	u_char vl_dp;		/* Data polarity */
> +	u_char vl_bpix;		/* Bits per pixel */
> +
> +	/* Horizontal control register. Timing from data sheet */
> +	u_char vl_hspw;		/* Horz sync pulse width */
> +	u_char vl_hfpd;		/* Wait before of line */
> +	u_char vl_hbpd;		/* Wait end of line */
> +
> +	/* Vertical control register. */
> +	u_char	vl_vspw;	/* Vertical sync pulse width */
> +	u_char	vl_vfpd;	/* Wait before of frame */
> +	u_char	vl_vbpd;	/* Wait end of frame */
> +	u_char  vl_cmd_allow_len; /* Wait end of frame */
> +
> +	unsigned int win_id;
> +	unsigned int init_delay;
> +	unsigned int power_on_delay;
> +	unsigned int reset_delay;
> +	unsigned int interface_mode;
> +	unsigned int mipi_enabled;
> +	unsigned int dp_enabled;
> +	unsigned int cs_setup;
> +	unsigned int wr_setup;
> +	unsigned int wr_act;
> +	unsigned int wr_hold;
> +	unsigned int logo_on;
> +	unsigned int logo_width;
> +	unsigned int logo_height;
> +	int logo_x_offset;
> +	int logo_y_offset;
> +	unsigned long logo_addr;
> +	unsigned int rgb_mode;
> +	unsigned int resolution;
> +
> +	/* parent clock name(MPLL, EPLL or VPLL) */
> +	unsigned int pclk_name;
> +	/* ratio value for source clock from parent clock. */
> +	unsigned int sclk_div;
> +
> +	unsigned int dual_lcd_enabled;
> +} vidinfo_t;
> +
> +void init_panel_info(vidinfo_t *vid);
> +
> +#endif
> diff --git a/include/lcd.h b/include/lcd.h
> index 160f940..fbba6a2 100644
> --- a/include/lcd.h
> +++ b/include/lcd.h
> @@ -41,205 +41,15 @@ int bmp_display(ulong addr, int x, int y);
>   void lcd_set_flush_dcache(int flush);
>
>   #if defined CONFIG_MPC823
> -/*
> - * LCD controller stucture for MPC823 CPU
> - */
> -typedef struct vidinfo {
> -	ushort	vl_col;		/* Number of columns (i.e. 640) */
> -	ushort	vl_row;		/* Number of rows (i.e. 480) */
> -	ushort	vl_width;	/* Width of display area in millimeters */
> -	ushort	vl_height;	/* Height of display area in millimeters */
> -
> -	/* LCD configuration register */
> -	u_char	vl_clkp;	/* Clock polarity */
> -	u_char	vl_oep;		/* Output Enable polarity */
> -	u_char	vl_hsp;		/* Horizontal Sync polarity */
> -	u_char	vl_vsp;		/* Vertical Sync polarity */
> -	u_char	vl_dp;		/* Data polarity */
> -	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
> -	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
> -	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
> -	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
> -	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
> -
> -	/* Horizontal control register. Timing from data sheet */
> -	ushort	vl_wbl;		/* Wait between lines */
> -
> -	/* Vertical control register */
> -	u_char	vl_vpw;		/* Vertical sync pulse width */
> -	u_char	vl_lcdac;	/* LCD AC timing */
> -	u_char	vl_wbf;		/* Wait between frames */
> -} vidinfo_t;
> -
> +#include <mpc823_lcd.h>
>   #elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
>   	defined CONFIG_CPU_MONAHANS
> -/*
> - * PXA LCD DMA descriptor
> - */
> -struct pxafb_dma_descriptor {
> -	u_long	fdadr;		/* Frame descriptor address register */
> -	u_long	fsadr;		/* Frame source address register */
> -	u_long	fidr;		/* Frame ID register */
> -	u_long	ldcmd;		/* Command register */
> -};
> -
> -/*
> - * PXA LCD info
> - */
> -struct pxafb_info {
> -
> -	/* Misc registers */
> -	u_long	reg_lccr3;
> -	u_long	reg_lccr2;
> -	u_long	reg_lccr1;
> -	u_long	reg_lccr0;
> -	u_long	fdadr0;
> -	u_long	fdadr1;
> -
> -	/* DMA descriptors */
> -	struct	pxafb_dma_descriptor *	dmadesc_fblow;
> -	struct	pxafb_dma_descriptor *	dmadesc_fbhigh;
> -	struct	pxafb_dma_descriptor *	dmadesc_palette;
> -
> -	u_long	screen;		/* physical address of frame buffer */
> -	u_long	palette;	/* physical address of palette memory */
> -	u_int	palette_size;
> -};
> -
> -/*
> - * LCD controller stucture for PXA CPU
> - */
> -typedef struct vidinfo {
> -	ushort	vl_col;		/* Number of columns (i.e. 640) */
> -	ushort	vl_row;		/* Number of rows (i.e. 480) */
> -	ushort	vl_width;	/* Width of display area in millimeters */
> -	ushort	vl_height;	/* Height of display area in millimeters */
> -
> -	/* LCD configuration register */
> -	u_char	vl_clkp;	/* Clock polarity */
> -	u_char	vl_oep;		/* Output Enable polarity */
> -	u_char	vl_hsp;		/* Horizontal Sync polarity */
> -	u_char	vl_vsp;		/* Vertical Sync polarity */
> -	u_char	vl_dp;		/* Data polarity */
> -	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
> -	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
> -	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
> -	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
> -	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
> -
> -	/* Horizontal control register. Timing from data sheet */
> -	ushort	vl_hpw;		/* Horz sync pulse width */
> -	u_char	vl_blw;		/* Wait before of line */
> -	u_char	vl_elw;		/* Wait end of line */
> -
> -	/* Vertical control register. */
> -	u_char	vl_vpw;		/* Vertical sync pulse width */
> -	u_char	vl_bfw;		/* Wait before of frame */
> -	u_char	vl_efw;		/* Wait end of frame */
> -
> -	/* PXA LCD controller params */
> -	struct	pxafb_info pxa;
> -} vidinfo_t;
> -
> +#include <pxa_lcd.h>
>   #elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
> -
> -typedef struct vidinfo {
> -	ushort vl_col;		/* Number of columns (i.e. 640) */
> -	ushort vl_row;		/* Number of rows (i.e. 480) */
> -	u_long vl_clk;	/* pixel clock in ps    */
> -
> -	/* LCD configuration register */
> -	u_long vl_sync;		/* Horizontal / vertical sync */
> -	u_long vl_bpix;		/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
> -	u_long vl_tft;		/* 0 = passive, 1 = TFT */
> -	u_long vl_cont_pol_low;	/* contrast polarity is low */
> -	u_long vl_clk_pol;	/* clock polarity */
> -
> -	/* Horizontal control register. */
> -	u_long vl_hsync_len;	/* Length of horizontal sync */
> -	u_long vl_left_margin;	/* Time from sync to picture */
> -	u_long vl_right_margin;	/* Time from picture to sync */
> -
> -	/* Vertical control register. */
> -	u_long vl_vsync_len;	/* Length of vertical sync */
> -	u_long vl_upper_margin;	/* Time from sync to picture */
> -	u_long vl_lower_margin;	/* Time from picture to sync */
> -
> -	u_long	mmio;		/* Memory mapped registers */
> -} vidinfo_t;
> -
> +#include <atmel_lcd.h>
>   #elif defined(CONFIG_EXYNOS_FB)
> -
> -enum {
> -	FIMD_RGB_INTERFACE = 1,
> -	FIMD_CPU_INTERFACE = 2,
> -};
> -
> -enum exynos_fb_rgb_mode_t {
> -	MODE_RGB_P = 0,
> -	MODE_BGR_P = 1,
> -	MODE_RGB_S = 2,
> -	MODE_BGR_S = 3,
> -};
> -
> -typedef struct vidinfo {
> -	ushort vl_col;		/* Number of columns (i.e. 640) */
> -	ushort vl_row;		/* Number of rows (i.e. 480) */
> -	ushort vl_width;	/* Width of display area in millimeters */
> -	ushort vl_height;	/* Height of display area in millimeters */
> -
> -	/* LCD configuration register */
> -	u_char vl_freq;		/* Frequency */
> -	u_char vl_clkp;		/* Clock polarity */
> -	u_char vl_oep;		/* Output Enable polarity */
> -	u_char vl_hsp;		/* Horizontal Sync polarity */
> -	u_char vl_vsp;		/* Vertical Sync polarity */
> -	u_char vl_dp;		/* Data polarity */
> -	u_char vl_bpix;		/* Bits per pixel */
> -
> -	/* Horizontal control register. Timing from data sheet */
> -	u_char vl_hspw;		/* Horz sync pulse width */
> -	u_char vl_hfpd;		/* Wait before of line */
> -	u_char vl_hbpd;		/* Wait end of line */
> -
> -	/* Vertical control register. */
> -	u_char	vl_vspw;	/* Vertical sync pulse width */
> -	u_char	vl_vfpd;	/* Wait before of frame */
> -	u_char	vl_vbpd;	/* Wait end of frame */
> -	u_char  vl_cmd_allow_len; /* Wait end of frame */
> -
> -	unsigned int win_id;
> -	unsigned int init_delay;
> -	unsigned int power_on_delay;
> -	unsigned int reset_delay;
> -	unsigned int interface_mode;
> -	unsigned int mipi_enabled;
> -	unsigned int dp_enabled;
> -	unsigned int cs_setup;
> -	unsigned int wr_setup;
> -	unsigned int wr_act;
> -	unsigned int wr_hold;
> -	unsigned int logo_on;
> -	unsigned int logo_width;
> -	unsigned int logo_height;
> -	int logo_x_offset;
> -	int logo_y_offset;
> -	unsigned long logo_addr;
> -	unsigned int rgb_mode;
> -	unsigned int resolution;
> -
> -	/* parent clock name(MPLL, EPLL or VPLL) */
> -	unsigned int pclk_name;
> -	/* ratio value for source clock from parent clock. */
> -	unsigned int sclk_div;
> -
> -	unsigned int dual_lcd_enabled;
> -} vidinfo_t;
> -
> -void init_panel_info(vidinfo_t *vid);
> -
> +#include <exynos_lcd.h>
>   #else
> -
>   typedef struct vidinfo {
>   	ushort	vl_col;		/* Number of columns (i.e. 160) */
>   	ushort	vl_row;		/* Number of rows (i.e. 100) */
> @@ -250,8 +60,7 @@ typedef struct vidinfo {
>
>   	void	*priv;		/* Pointer to driver-specific data */
>   } vidinfo_t;
> -
> -#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */
> +#endif
>
>   extern vidinfo_t panel_info;
>
> diff --git a/include/mpc823_lcd.h b/include/mpc823_lcd.h
> new file mode 100644
> index 0000000..7e210e3
> --- /dev/null
> +++ b/include/mpc823_lcd.h
> @@ -0,0 +1,43 @@
> +/*
> + * mpc823_lcd.h - MPC823 LCD Controller structures
> + *
> + * (C) Copyright 2001
> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef _MPC823_LCD_H_
> +#define _MPC823_LCD_H_
> +
> +/*
> + * LCD controller stucture for MPC823 CPU
> + */
> +typedef struct vidinfo {
> +	ushort	vl_col;		/* Number of columns (i.e. 640) */
> +	ushort	vl_row;		/* Number of rows (i.e. 480) */
> +	ushort	vl_width;	/* Width of display area in millimeters */
> +	ushort	vl_height;	/* Height of display area in millimeters */
> +
> +	/* LCD configuration register */
> +	u_char	vl_clkp;	/* Clock polarity */
> +	u_char	vl_oep;		/* Output Enable polarity */
> +	u_char	vl_hsp;		/* Horizontal Sync polarity */
> +	u_char	vl_vsp;		/* Vertical Sync polarity */
> +	u_char	vl_dp;		/* Data polarity */
> +	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
> +	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
> +	u_char	vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
> +	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
> +	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
> +
> +	/* Horizontal control register. Timing from data sheet */
> +	ushort	vl_wbl;		/* Wait between lines */
> +
> +	/* Vertical control register */
> +	u_char	vl_vpw;		/* Vertical sync pulse width */
> +	u_char	vl_lcdac;	/* LCD AC timing */
> +	u_char	vl_wbf;		/* Wait between frames */
> +} vidinfo_t;
> +
> +#endif
> diff --git a/include/pxa_lcd.h b/include/pxa_lcd.h
> new file mode 100644
> index 0000000..723f6ab
> --- /dev/null
> +++ b/include/pxa_lcd.h
> @@ -0,0 +1,80 @@
> +/*
> + * pxa_lcd.h - PXA LCD Controller structures
> + *
> + * (C) Copyright 2001
> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef _PXA_LCD_H_
> +#define _PXA_LCD_H_
> +
> +/*
> + * PXA LCD DMA descriptor
> + */
> +struct pxafb_dma_descriptor {
> +	u_long	fdadr;		/* Frame descriptor address register */
> +	u_long	fsadr;		/* Frame source address register */
> +	u_long	fidr;		/* Frame ID register */
> +	u_long	ldcmd;		/* Command register */
> +};
> +
> +/*
> + * PXA LCD info
> + */
> +struct pxafb_info {
> +	/* Misc registers */
> +	u_long	reg_lccr3;
> +	u_long	reg_lccr2;
> +	u_long	reg_lccr1;
> +	u_long	reg_lccr0;
> +	u_long	fdadr0;
> +	u_long	fdadr1;
> +
> +	/* DMA descriptors */
> +	struct	pxafb_dma_descriptor *dmadesc_fblow;
> +	struct	pxafb_dma_descriptor *dmadesc_fbhigh;
> +	struct	pxafb_dma_descriptor *dmadesc_palette;
> +
> +	u_long	screen;		/* physical address of frame buffer */
> +	u_long	palette;	/* physical address of palette memory */
> +	u_int	palette_size;
> +};
> +
> +/*
> + * LCD controller stucture for PXA CPU
> + */
> +typedef struct vidinfo {
> +	ushort	vl_col;		/* Number of columns (i.e. 640) */
> +	ushort	vl_row;		/* Number of rows (i.e. 480) */
> +	ushort	vl_width;	/* Width of display area in millimeters */
> +	ushort	vl_height;	/* Height of display area in millimeters */
> +
> +	/* LCD configuration register */
> +	u_char	vl_clkp;	/* Clock polarity */
> +	u_char	vl_oep;		/* Output Enable polarity */
> +	u_char	vl_hsp;		/* Horizontal Sync polarity */
> +	u_char	vl_vsp;		/* Vertical Sync polarity */
> +	u_char	vl_dp;		/* Data polarity */
> +	u_char	vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
> +	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
> +	u_char	vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */
> +	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
> +	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
> +
> +	/* Horizontal control register. Timing from data sheet */
> +	ushort	vl_hpw;		/* Horz sync pulse width */
> +	u_char	vl_blw;		/* Wait before of line */
> +	u_char	vl_elw;		/* Wait end of line */
> +
> +	/* Vertical control register. */
> +	u_char	vl_vpw;		/* Vertical sync pulse width */
> +	u_char	vl_bfw;		/* Wait before of frame */
> +	u_char	vl_efw;		/* Wait end of frame */
> +
> +	/* PXA LCD controller params */
> +	struct	pxafb_info pxa;
> +} vidinfo_t;
> +
> +#endif
>