From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v2 3/9] xen: arm: Handle 32-bit EL0 on 64-bit EL1 when advancing PC after trap Date: Tue, 10 Feb 2015 13:44:08 +0800 Message-ID: <54D99AA8.4050608@linaro.org> References: <1423542956.5851.9.camel@citrix.com> <1423543523-8010-3-git-send-email-ian.campbell@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1423543523-8010-3-git-send-email-ian.campbell@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , xen-devel@lists.xen.org Cc: tim@xen.org, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Hi Ian, On 10/02/2015 12:45, Ian Campbell wrote: > Signed-off-by: Ian Campbell > Reviewed-by: Julien Grall > --- > xen/arch/arm/traps.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > index c5f65db..be65862 100644 > --- a/xen/arch/arm/traps.c > +++ b/xen/arch/arm/traps.c > @@ -1487,7 +1487,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, union hsr hsr) > { > unsigned long it; > > - BUG_ON( !is_32bit_domain(current->domain) || !(cpsr&PSR_THUMB) ); > + BUG_ON( !psr_mode_is_32bit(regs->cpsr) || !(cpsr&PSR_THUMB) ); > > it = ( (cpsr >> (10-2)) & 0xfc) | ((cpsr >> 25) & 0x3 ); > > @@ -1496,7 +1496,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, union hsr hsr) > return 1; > > /* The cond for this instruction works out as the top 4 bits. */ > - cond = ( it >> 4 ); > + cond = ( it >> 4 ); I haven't spot it in the previous review. This seems to be only a coding change. Could you specify it in the commit message? Regards, -- Julien Grall