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From: Zhi Wang <zhi.a.wang@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>, david.s.gordon@intel.com
Cc: intel-gfx@lists.freedesktop.org,
	orprtsshouldn'tupdateuntiltestshavebeenvetted@phenom.ffwll.local
Subject: Re: [PATCH] drm/i915: Introduce bit definitions of CTXT_SR_CTRL register.
Date: Wed, 11 Feb 2015 00:36:48 +0800	[thread overview]
Message-ID: <54DA33A0.5050804@intel.com> (raw)
In-Reply-To: <20150211080330.GB24485@phenom.ffwll.local>

Thanks Daniel! :)

于 2015年02月11日 16:03, Daniel Vetter 写道:
> On Tue, Feb 10, 2015 at 05:11:36PM +0800, Zhi Wang wrote:
>> This patch introduces 2 bit definitions of context save/restore
>> control register.
>>
>> Thanks comments from David/Thomas/Daniel.
>
> Instead of Thanks just add the usual Suggested-by: lines. And please Cc:
> everyone from the previous discussion when you follow up with a patch.
> I've added that now.
>>
>> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
>
> Queued for -next, thanks for the patch.
> -Daniel
>
>> ---
>>   drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
>>   drivers/gpu/drm/i915/intel_lrc.h | 2 ++
>>   2 files changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index d05f3bc..2196e9c 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1668,7 +1668,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
>>   	reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
>>   	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
>>   	reg_state[CTX_CONTEXT_CONTROL+1] =
>> -			_MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
>> +		_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
>> +				CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
>>   	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
>>   	reg_state[CTX_RING_HEAD+1] = 0;
>>   	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
>> index 6f2d7da..ced191f 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.h
>> +++ b/drivers/gpu/drm/i915/intel_lrc.h
>> @@ -30,6 +30,8 @@
>>   #define RING_ELSP(ring)			((ring)->mmio_base+0x230)
>>   #define RING_EXECLIST_STATUS(ring)	((ring)->mmio_base+0x234)
>>   #define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
>> +#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
>> +#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
>>   #define RING_CONTEXT_STATUS_BUF(ring)	((ring)->mmio_base+0x370)
>>   #define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)
>>
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

      reply	other threads:[~2015-02-11  8:05 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-10  9:11 [PATCH] drm/i915: Introduce bit definitions of CTXT_SR_CTRL register Zhi Wang
2015-02-11  8:03 ` Daniel Vetter
2015-02-10 16:36   ` Zhi Wang [this message]

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