From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51438) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLvqp-0002k3-8W for qemu-devel@nongnu.org; Thu, 12 Feb 2015 10:38:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YLvqj-0004xH-MS for qemu-devel@nongnu.org; Thu, 12 Feb 2015 10:38:46 -0500 Received: from cantor2.suse.de ([195.135.220.15]:42077 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLvqj-0004x2-FX for qemu-devel@nongnu.org; Thu, 12 Feb 2015 10:38:41 -0500 Message-ID: <54DCC8FF.7000609@suse.de> Date: Thu, 12 Feb 2015 16:38:39 +0100 From: Alexander Graf MIME-Version: 1.0 References: <31B94C07-29A9-4595-95ED-FA860B527BD8@suse.de> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] Help on TLB Flush List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: mttcg@listserver.greensocs.com, Mark Burton , qemu-devel On 12.02.15 15:58, Peter Maydell wrote: > On 12 February 2015 at 14:45, Alexander Graf wrote: >> almost nobody except x86 does global flushes >=20 > All ARM TLB maintenance operations have both "this CPU only" > and "all TLBs in the Inner Shareable domain" [that's ARM-speak > for "every CPU core in the cluster"] variants (the latter > being the TLB *IS operations). Looking at Linux's > arch/arm64/mm/tlb.S and arch/arm64/include/asm/tlbflush.h > most of the operations defined there use the IS variants. Wow, did anyone benchmark this? I know that PPC switched away from global flushes and instead tracks the CPUs a task was running on to limit the scope of CPUs that need to flush. Alex