From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51820) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YMCeM-0002WA-ED for qemu-devel@nongnu.org; Fri, 13 Feb 2015 04:35:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YMCeI-0007Qr-CX for qemu-devel@nongnu.org; Fri, 13 Feb 2015 04:35:02 -0500 Received: from mx1.redhat.com ([209.132.183.28]:45457) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YMCeI-0007Qn-55 for qemu-devel@nongnu.org; Fri, 13 Feb 2015 04:34:58 -0500 Message-ID: <54DDC537.5070003@redhat.com> Date: Fri, 13 Feb 2015 10:34:47 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: <31B94C07-29A9-4595-95ED-FA860B527BD8@suse.de> <45883806-2296-486F-A0DC-D8A0A74F85B9@greensocs.com> <54DCC494.2010400@suse.de> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] Help on TLB Flush List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , Alexander Graf Cc: mttcg@greensocs.com, Mark Burton , qemu-devel On 12/02/2015 22:57, Peter Maydell wrote: > The only > requirement is that if the CPU that did the TLB maintenance > op executes a DMB (barrier) then the TLB op must finish > before the barrier completes execution. So you could split > the "kick off TLB invalidate" and "make sure all CPUs > are done" phases if you wanted. [cf v8 ARM ARM rev A.e > section D4.7.2 and in particular the subsection on > "ordering and completion".] You can just make DMB start a new translation block. Then when the TLB flush helpers call cpu_exit() or cpu_interrupt() the flush request is serviced. Paolo