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Date: Tue, 17 Feb 2015 06:51:49 +0800
From: Chen Gang S <gang.chen@sunrus.com.cn>
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Subject: Re: [Qemu-devel] [PATCH 1/6 v2] target-tilegx: Firstly add to qemu
 with minimized features
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To: Richard Henderson <rth@twiddle.net>, Peter Maydell <peter.maydell@linaro.org>, Chris Metcalf <cmetcalf@ezchip.com>, Riku Voipio <riku.voipio@iki.fi>, "walt@tilera.com" <walt@tilera.com>
Cc: qemu-devel <qemu-devel@nongnu.org>

On 2/17/15 00:25, Richard Henderson wrote:
> On 02/16/2015 05:49 AM, Chen Gang S wrote:
>> +#define TILEGX_R_PC  55  /* LR register, pc pointer */
> 
> No, register 55 is the link register, not the PC.
> I.e. it is only special in that it receives the
> return address from the JAL instructions.
> 
>> +typedef struct CPUTLState {
>> +    uint64_t regs[56];
>> +    CPU_COMMON
>> +} CPUTLState;
> 
> Which means you need another entry here for the PC.
> 
>> +static inline void cpu_get_tb_cpu_state(CPUTLState *env, target_ulong *pc,
>> +                                        target_ulong *cs_base, int *flags)
>> +{
>> +    *pc = env->regs[TILEGX_R_PC];
> 
> And you should not reference the link register here.
> 
> 

OK, thanks. What you said sound reasonable to me. I shall send patch v3
if no any additiona reply for patch v2 within 3 days (2015-02-20).

And excuse me, I still want to know, is there a real world register as a
PC register for tile (e.g. just like 'rip' for x86_64) which can be used
by software programer? (is it in SPR?)

Thanks.
-- 
Chen Gang

Open, share, and attitude like air, water, and life which God blessed