From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@linaro.org>
Subject: Re: [PATCH v2 7/9] xen: arm: correctly handle sysreg
 accesses from userspace
Date: Tue, 17 Feb 2015 15:25:16 +0000
Message-ID: <54E35D5C.9090500@linaro.org>
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	<1423543523-8010-7-git-send-email-ian.campbell@citrix.com>
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Hi Ian,

On 10/02/15 04:45, Ian Campbell wrote:
> Previously we implemented all registers as RAZ/WI even if they
> shouldn't be accessible to userspace.
> 
> Accesses to the *_EL1 registers from EL0 are trapped to EL1 by the
> hardware, so add a BUG_ON. Likewise accesses from 32-bit EL1 cannot
> happen.
> 
> PMUSERENR_EL0 and MDCCSR_EL0 are R/O to EL0.
> 
> Other PM*_EL0 registers are accessible at EL0 only if
> PMUSERENR_EL0.EN is set, since we emulate that as RAZ/WI we know that
> bit cannot be set.

You assume that PMUSERENR_EL0.EN is always set to 0 during Xen boot.
Actually it's not the case and from the spec, it may be possible to have
it in an unkwnown state.

Regards,

-- 
Julien Grall