From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH 2/2] xen: arm: Warn if timer interrupts are not level triggered Date: Thu, 19 Feb 2015 16:20:18 +0000 Message-ID: <54E60D42.7060405@linaro.org> References: <1424359395.30924.89.camel@citrix.com> <1424359443-21584-2-git-send-email-ian.campbell@citrix.com> <54E6041C.6020300@linaro.org> <1424362240.30924.110.camel@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1424362240.30924.110.camel@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: stefano.stabellini@eu.citrix.com, tim@xen.org, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 19/02/15 16:10, Ian Campbell wrote: > On Thu, 2015-02-19 at 15:41 +0000, Julien Grall wrote: >>> I did consider overriding the incorrect DT on such systems but since >>> so far it has only been observed on emulators and we have code in >>> place to deal with edge triggering here I think warning is sufficient >>> for now. > [...] >>> + * >>> + * Check each interrupt and warn if we find ourselves in this situation. >>> + */ >> >> Based on the comment, would it make sense to override the type of >> interrupt to level in anycase? Even if the GIC allows us to write on ICFGR. > > See the comment in the commit message (quoted above) Sorry, I skipped this part of the commit message. I wasn't not sure there is others issues that we don't have spot because of the edge interrupt. Regardless the question,this patch look good to me. With the 2 nits I spotted on my previous email: Reviewed-by: Julien Grall Regards, -- Julien Grall