From: Paolo Bonzini <pbonzini@redhat.com>
To: Alexander Graf <agraf@suse.de>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 3/3] target-ppc: use separate indices for various translation modes
Date: Fri, 20 Feb 2015 18:58:58 +0100 [thread overview]
Message-ID: <54E775E2.4040005@redhat.com> (raw)
In-Reply-To: <54E73001.8000104@suse.de>
On 20/02/2015 14:00, Alexander Graf wrote:
> Also please double-check that 440 still works. That was the target that
> gave me the most headaches on DR/IR switching so far.
The ppc-virtexml507-linux-2_6_34.tgz image works for me.
Paolo
> Otherwise looks simple and clean to me :).
>
>
> Alex
>
>> }
>>
>> static inline void hreg_compute_hflags(CPUPPCState *env)
>> @@ -56,7 +59,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env)
>> /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
>> hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
>> (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
>> - (1 << MSR_LE) | (1 << MSR_VSX);
>> + (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
>> hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
>> hreg_compute_mem_idx(env);
>> env->hflags = env->msr & hflags_mask;
>> @@ -82,8 +85,6 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
>> }
>> if (((value >> MSR_IR) & 1) != msr_ir ||
>> ((value >> MSR_DR) & 1) != msr_dr) {
>> - /* Flush all tlb when changing translation mode */
>> - tlb_flush(cs, 1);
>> excp = POWERPC_EXCP_NONE;
>> cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
>> }
>>
>
>
next prev parent reply other threads:[~2015-02-20 17:59 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-20 12:45 [Qemu-devel] [PATCH for-2.3 0/3] Support more than 8 MMU modes, speedup by 10% Paolo Bonzini
2015-02-20 12:45 ` [Qemu-devel] [PATCH 1/3] tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS Paolo Bonzini
2015-02-20 12:45 ` [Qemu-devel] [PATCH 2/3] softmmu: support up to 12 MMU modes Paolo Bonzini
2015-02-20 12:45 ` [Qemu-devel] [PATCH 3/3] target-ppc: use separate indices for various translation modes Paolo Bonzini
2015-02-20 13:00 ` Alexander Graf
2015-02-20 17:58 ` Paolo Bonzini [this message]
-- strict thread matches above, loose matches on Subject: below --
2015-02-20 17:57 [Qemu-devel] [PATCH v2 for-2.3 0/3] Support more than 8 MMU modes, speedup PPC by 10% Paolo Bonzini
2015-02-20 17:57 ` [Qemu-devel] [PATCH 3/3] target-ppc: use separate indices for various translation modes Paolo Bonzini
2015-02-20 19:54 ` Richard Henderson
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