Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA I/O.

[Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>]

On 02/24/2015 02:50 PM, Maciej W. Rozycki wrote:
> On Tue, 24 Feb 2015, Leonid Yegoshin wrote:
>
>>>    For simplicity perhaps on SMP we should just always use hit operations
>>> regardless of the size requested.
>> High performance folks may not like doing a lot of stuff for 8MB VMA release
>> instead of flushing 64KB.
>   What kind of a use case is that, what does it do?
>
>
cacheflush() calls flush_icache_range(). And we see:

linux-yegoshin:/space/yegoshin/MIPS-kernel/linux-mips.org/linux-mti% gid 
flush_icache_range | grep -v arch/
include/asm-generic/cacheflush.h:20:#define flush_icache_range(start, 
end)        do { } while (0)
fs/binfmt_flat.c:787:    flush_icache_range(start_code, end_code);
fs/exec.c:823:        flush_icache_range(addr, addr + len);
kernel/module.c:2886:        flush_icache_range((unsigned 
long)mod->module_init,
kernel/module.c:2889:    flush_icache_range((unsigned long)mod->module_core,
mm/nommu.c:532:    flush_icache_range(mm->brk, brk);
mm/nommu.c:1441:        flush_icache_range(region->vm_start, 
region->vm_end);
drivers/misc/lkdtm.c:346:    flush_icache_range((unsigned long)dst, 
(unsigned long)dst + EXEC_SIZE);
drivers/misc/lkdtm.c:361:    flush_icache_range((unsigned long)dst, 
(unsigned long)dst + EXEC_SIZE);
drivers/misc/lkdtm.c:519:        flush_icache_range((unsigned long)ptr,
kernel/debug/debug_core.c:243:    flush_icache_range(addr, addr + 
BREAK_INSTR_SIZE);
kernel/debug/gdbstub.c:383:            flush_icache_range(addr, addr + 
length);
drivers/video/console/sticore.c:254:    flush_icache_range(start, end);
Documentation/cachetlb.txt:369:  void flush_icache_range(unsigned long 
start, unsigned long end)

It is not for VMA release, I was wrong here, but there are still some 
interesting use cases for flush_icache_range().


Note: it is not cacheflush() bug, it is bug in r4k_on_each_cpu(). I have 
a patch named

Author: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Date:   Mon Apr 1 20:10:30 2013 -0700

     MIPS: Cache flush functions are reworked.

     This patch is a preparation for EVA support in kernel.

     However, it also fixes a bug then index cacheop was not ran
     on multiple CPUs with unsafe index cacheops (flush_cache_vmap,
     flush_icache_range, flush_cache_range, __flush_cache_all).

     Additionally, it optimizes a usage of index and address cacheops for
     address range flushes depending from address range size.

     Because of that reasons it is a separate patch from EVA support.

     Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
     Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
     (cherry picked from commit 6b05dd71da1136fbad0ce642790c4c99343f05e7)

but it is still doesn't go through LMO.

- Leonid.