From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tero Kristo Subject: Re: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes Date: Wed, 25 Feb 2015 09:28:48 +0200 Message-ID: <54ED79B0.4020101@ti.com> References: <1422724005-9415-1-git-send-email-rk@ti.com> <54E5FC6D.7040701@ti.com> <20150224162719.GA28244@atomide.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20150224162719.GA28244@atomide.com> Sender: linux-kernel-owner@vger.kernel.org To: Tony Lindgren , Ravikumar Kattekola Cc: bcousson@baylibre.com, mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: linux-omap@vger.kernel.org On 02/24/2015 06:27 PM, Tony Lindgren wrote: > * Ravikumar Kattekola [150219 08:13]: >> On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote: >>> Fix bypass clock source for a few DPLLs. >>> >>> On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected >>> to a mux and the output from mux is routed to the bypass clkout. >>> Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents. >>> >>> Tested against: >>> tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git >>> branch: master >>> On: >>> CPU : OMAP5432 ES2.0 >>> Board: OMAP5432 uEVM >>> and >>> CPU : DRA752 ES1.0 >>> Board: DRA7xx >>> >>> >>> Ravikumar Kattekola (2): >>> ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others >>> ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others >>> >>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 90 ++++++++++++++++++++++++++++---- >>> arch/arm/boot/dts/omap54xx-clocks.dtsi | 41 +++++++++++++-- >>> 2 files changed, 118 insertions(+), 13 deletions(-) >>> >> Hi Benoit, >> Can these fixes be looked into for 3.20-rc? > > Seem like valid fixes to me. Tero, care to take a look at these and ack > if OK? Yes, both are good to go. Acked-by: Tero Kristo From mboxrd@z Thu Jan 1 00:00:00 1970 From: t-kristo@ti.com (Tero Kristo) Date: Wed, 25 Feb 2015 09:28:48 +0200 Subject: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes In-Reply-To: <20150224162719.GA28244@atomide.com> References: <1422724005-9415-1-git-send-email-rk@ti.com> <54E5FC6D.7040701@ti.com> <20150224162719.GA28244@atomide.com> Message-ID: <54ED79B0.4020101@ti.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 02/24/2015 06:27 PM, Tony Lindgren wrote: > * Ravikumar Kattekola [150219 08:13]: >> On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote: >>> Fix bypass clock source for a few DPLLs. >>> >>> On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected >>> to a mux and the output from mux is routed to the bypass clkout. >>> Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents. >>> >>> Tested against: >>> tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git >>> branch: master >>> On: >>> CPU : OMAP5432 ES2.0 >>> Board: OMAP5432 uEVM >>> and >>> CPU : DRA752 ES1.0 >>> Board: DRA7xx >>> >>> >>> Ravikumar Kattekola (2): >>> ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others >>> ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others >>> >>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 90 ++++++++++++++++++++++++++++---- >>> arch/arm/boot/dts/omap54xx-clocks.dtsi | 41 +++++++++++++-- >>> 2 files changed, 118 insertions(+), 13 deletions(-) >>> >> Hi Benoit, >> Can these fixes be looked into for 3.20-rc? > > Seem like valid fixes to me. Tero, care to take a look at these and ack > if OK? Yes, both are good to go. Acked-by: Tero Kristo From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752545AbbBYH3P (ORCPT ); Wed, 25 Feb 2015 02:29:15 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:51620 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750761AbbBYH3N (ORCPT ); Wed, 25 Feb 2015 02:29:13 -0500 Message-ID: <54ED79B0.4020101@ti.com> Date: Wed, 25 Feb 2015 09:28:48 +0200 From: Tero Kristo User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: Tony Lindgren , Ravikumar Kattekola CC: , , , , , , , , , , Subject: Re: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes References: <1422724005-9415-1-git-send-email-rk@ti.com> <54E5FC6D.7040701@ti.com> <20150224162719.GA28244@atomide.com> In-Reply-To: <20150224162719.GA28244@atomide.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/24/2015 06:27 PM, Tony Lindgren wrote: > * Ravikumar Kattekola [150219 08:13]: >> On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote: >>> Fix bypass clock source for a few DPLLs. >>> >>> On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected >>> to a mux and the output from mux is routed to the bypass clkout. >>> Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents. >>> >>> Tested against: >>> tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git >>> branch: master >>> On: >>> CPU : OMAP5432 ES2.0 >>> Board: OMAP5432 uEVM >>> and >>> CPU : DRA752 ES1.0 >>> Board: DRA7xx >>> >>> >>> Ravikumar Kattekola (2): >>> ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others >>> ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others >>> >>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 90 ++++++++++++++++++++++++++++---- >>> arch/arm/boot/dts/omap54xx-clocks.dtsi | 41 +++++++++++++-- >>> 2 files changed, 118 insertions(+), 13 deletions(-) >>> >> Hi Benoit, >> Can these fixes be looked into for 3.20-rc? > > Seem like valid fixes to me. Tero, care to take a look at these and ack > if OK? Yes, both are good to go. Acked-by: Tero Kristo