* [PATCH 2/4] drm/dp: add DPCD definitions from DP 1.2a
2015-02-25 12:46 [PATCH 1/4] drm/dp: indentation and ordering cleanups Jani Nikula
@ 2015-02-25 12:46 ` Jani Nikula
2015-02-26 9:52 ` sonika
2015-02-25 12:46 ` [PATCH 3/4] drm/dp: add DPCD definitions from eDP 1.2 Jani Nikula
` (2 subsequent siblings)
3 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2015-02-25 12:46 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 95 ++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 90 insertions(+), 5 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 98fefe45d158..209c5b91b0e8 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -92,6 +92,15 @@
# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
# define DP_OUI_SUPPORT (1 << 7)
+#define DP_RECEIVE_PORT_0_CAP_0 0x008 /* XXX 1.2? */
+# define DP_LOCAL_EDID_PRESENT (1 << 1)
+# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
+
+#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
+
+#define DP_RECEIVE_PORT_1_CAP_0 0x00a
+#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
+
#define DP_I2C_SPEED_CAP 0x00c /* DPI */
# define DP_I2C_SPEED_1K 0x01
# define DP_I2C_SPEED_5K 0x02
@@ -101,10 +110,16 @@
# define DP_I2C_SPEED_1M 0x20
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
+# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
+# define DP_FRAMING_CHANGE_CAP (1 << 1)
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
+#define DP_ADAPTER_CAP 0x00f /* 1.2 */
+# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
+# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
+
#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
@@ -115,6 +130,44 @@
#define DP_MSTM_CAP 0x021 /* 1.2 */
# define DP_MST_CAP (1 << 0)
+#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
+
+/* AV_SYNC_DATA_BLOCK 1.2 */
+#define DP_AV_GRANULARITY 0x023
+# define DP_AG_FACTOR_MASK (0xf << 0)
+# define DP_AG_FACTOR_3MS (0 << 0)
+# define DP_AG_FACTOR_2MS (1 << 0)
+# define DP_AG_FACTOR_1MS (2 << 0)
+# define DP_AG_FACTOR_500US (3 << 0)
+# define DP_AG_FACTOR_200US (4 << 0)
+# define DP_AG_FACTOR_100US (5 << 0)
+# define DP_AG_FACTOR_10US (6 << 0)
+# define DP_AG_FACTOR_1US (7 << 0)
+# define DP_VG_FACTOR_MASK (0xf << 4)
+# define DP_VG_FACTOR_3MS (0 << 4)
+# define DP_VG_FACTOR_2MS (1 << 4)
+# define DP_VG_FACTOR_1MS (2 << 4)
+# define DP_VG_FACTOR_500US (3 << 4)
+# define DP_VG_FACTOR_200US (4 << 4)
+# define DP_VG_FACTOR_100US (5 << 4)
+
+#define DP_AUD_DEC_LAT0 0x024
+#define DP_AUD_DEC_LAT1 0x025
+
+#define DP_AUD_PP_LAT0 0x026
+#define DP_AUD_PP_LAT1 0x027
+
+#define DP_VID_INTER_LAT 0x028
+
+#define DP_VID_PROG_LAT 0x029
+
+#define DP_REP_LAT 0x02a
+
+#define DP_AUD_DEL_INS0 0x02b
+#define DP_AUD_DEL_INS1 0x02c
+#define DP_AUD_DEL_INS2 0x02d
+/* End of AV_SYNC_DATA_BLOCK */
+
#define DP_GUID 0x030 /* 1.2 */
#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
@@ -173,11 +226,12 @@
# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
# define DP_TRAINING_PATTERN_MASK 0x3
-# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
-# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
-# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
-# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
-# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
+/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
+# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
+# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
+# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
+# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
+# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
@@ -220,14 +274,45 @@
/* bitmask as for DP_I2C_SPEED_CAP */
#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
+# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
+# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
+# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
+
+#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
+#define DP_LINK_QUAL_LANE1_SET 0x10c
+#define DP_LINK_QUAL_LANE2_SET 0x10d
+#define DP_LINK_QUAL_LANE3_SET 0x10e
+# define DP_LINK_QUAL_PATTERN_DISABLE 0
+# define DP_LINK_QUAL_PATTERN_D10_2 1
+# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
+# define DP_LINK_QUAL_PATTERN_PRBS7 3
+# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
+# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
+# define DP_LINK_QUAL_PATTERN_MASK 7
+
+#define DP_TRAINING_LANE0_1_SET2 0x10f
+# define DP_LANE0_POST_CURSOR2_SET_MASK (3 << 0)
+# define DP_LANE0_MAX_POST_CURSOR2_REACHED (1 << 2)
+# define DP_LANE1_POST_CURSOR2_SET_MASK (3 << 4)
+# define DP_LANE1_MAX_POST_CURSOR2_REACHED (1 << 6)
+
+#define DP_TRAINING_LANE2_3_SET2 0x110
+/* bits as in DP_TRAINING_LANE0_1_SET2, but for lanes 2 and 3 */
#define DP_MSTM_CTRL 0x111 /* 1.2 */
# define DP_MST_EN (1 << 0)
# define DP_UP_REQ_EN (1 << 1)
# define DP_UPSTREAM_IS_SRC (1 << 2)
+#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
+#define DP_AUDIO_DELAY1 0x113
+#define DP_AUDIO_DELAY2 0x114
+
#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
+#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
+# define DP_PWR_NOT_NEEDED (1 << 0)
+
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE (1 << 0)
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 2/4] drm/dp: add DPCD definitions from DP 1.2a
2015-02-25 12:46 ` [PATCH 2/4] drm/dp: add DPCD definitions from DP 1.2a Jani Nikula
@ 2015-02-26 9:52 ` sonika
0 siblings, 0 replies; 17+ messages in thread
From: sonika @ 2015-02-26 9:52 UTC (permalink / raw)
To: Jani Nikula, dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/drm/drm_dp_helper.h | 95 ++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 90 insertions(+), 5 deletions(-)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 98fefe45d158..209c5b91b0e8 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -92,6 +92,15 @@
> # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
> # define DP_OUI_SUPPORT (1 << 7)
>
> +#define DP_RECEIVE_PORT_0_CAP_0 0x008 /* XXX 1.2? */
This is part of DPv1.1 as well, the 1.2 in comment stands for DP version?
> +# define DP_LOCAL_EDID_PRESENT (1 << 1)
> +# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
> +
> +#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
> +
> +#define DP_RECEIVE_PORT_1_CAP_0 0x00a
> +#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
> +
> #define DP_I2C_SPEED_CAP 0x00c /* DPI */
> # define DP_I2C_SPEED_1K 0x01
> # define DP_I2C_SPEED_5K 0x02
> @@ -101,10 +110,16 @@
> # define DP_I2C_SPEED_1M 0x20
>
> #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
> +# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
> +# define DP_FRAMING_CHANGE_CAP (1 << 1)
> # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
>
> #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
>
> +#define DP_ADAPTER_CAP 0x00f /* 1.2 */
> +# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
> +# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
> +
> #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
> # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
>
> @@ -115,6 +130,44 @@
> #define DP_MSTM_CAP 0x021 /* 1.2 */
> # define DP_MST_CAP (1 << 0)
>
> +#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
> +
> +/* AV_SYNC_DATA_BLOCK 1.2 */
> +#define DP_AV_GRANULARITY 0x023
> +# define DP_AG_FACTOR_MASK (0xf << 0)
> +# define DP_AG_FACTOR_3MS (0 << 0)
> +# define DP_AG_FACTOR_2MS (1 << 0)
> +# define DP_AG_FACTOR_1MS (2 << 0)
> +# define DP_AG_FACTOR_500US (3 << 0)
> +# define DP_AG_FACTOR_200US (4 << 0)
> +# define DP_AG_FACTOR_100US (5 << 0)
> +# define DP_AG_FACTOR_10US (6 << 0)
> +# define DP_AG_FACTOR_1US (7 << 0)
> +# define DP_VG_FACTOR_MASK (0xf << 4)
> +# define DP_VG_FACTOR_3MS (0 << 4)
> +# define DP_VG_FACTOR_2MS (1 << 4)
> +# define DP_VG_FACTOR_1MS (2 << 4)
> +# define DP_VG_FACTOR_500US (3 << 4)
> +# define DP_VG_FACTOR_200US (4 << 4)
> +# define DP_VG_FACTOR_100US (5 << 4)
> +
> +#define DP_AUD_DEC_LAT0 0x024
> +#define DP_AUD_DEC_LAT1 0x025
> +
> +#define DP_AUD_PP_LAT0 0x026
> +#define DP_AUD_PP_LAT1 0x027
> +
> +#define DP_VID_INTER_LAT 0x028
> +
> +#define DP_VID_PROG_LAT 0x029
> +
> +#define DP_REP_LAT 0x02a
> +
> +#define DP_AUD_DEL_INS0 0x02b
> +#define DP_AUD_DEL_INS1 0x02c
> +#define DP_AUD_DEL_INS2 0x02d
> +/* End of AV_SYNC_DATA_BLOCK */
> +
> #define DP_GUID 0x030 /* 1.2 */
>
> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> @@ -173,11 +226,12 @@
> # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
> # define DP_TRAINING_PATTERN_MASK 0x3
>
> -# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
> -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
> -# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
> -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
> -# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
> +/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
> +# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
> +# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
> +# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
> +# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
> +# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
>
> # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
> # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
> @@ -220,14 +274,45 @@
> /* bitmask as for DP_I2C_SPEED_CAP */
>
> #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
> +# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
> +# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
> +# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
> +
> +#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
> +#define DP_LINK_QUAL_LANE1_SET 0x10c
> +#define DP_LINK_QUAL_LANE2_SET 0x10d
> +#define DP_LINK_QUAL_LANE3_SET 0x10e
> +# define DP_LINK_QUAL_PATTERN_DISABLE 0
> +# define DP_LINK_QUAL_PATTERN_D10_2 1
> +# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
> +# define DP_LINK_QUAL_PATTERN_PRBS7 3
> +# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
> +# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
> +# define DP_LINK_QUAL_PATTERN_MASK 7
> +
> +#define DP_TRAINING_LANE0_1_SET2 0x10f
> +# define DP_LANE0_POST_CURSOR2_SET_MASK (3 << 0)
> +# define DP_LANE0_MAX_POST_CURSOR2_REACHED (1 << 2)
> +# define DP_LANE1_POST_CURSOR2_SET_MASK (3 << 4)
> +# define DP_LANE1_MAX_POST_CURSOR2_REACHED (1 << 6)
> +
> +#define DP_TRAINING_LANE2_3_SET2 0x110
> +/* bits as in DP_TRAINING_LANE0_1_SET2, but for lanes 2 and 3 */
>
Since bits are same, do you want to add 2 and 3 to the corresponding
macro above?
You can take a call.
> #define DP_MSTM_CTRL 0x111 /* 1.2 */
> # define DP_MST_EN (1 << 0)
> # define DP_UP_REQ_EN (1 << 1)
> # define DP_UPSTREAM_IS_SRC (1 << 2)
>
> +#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
> +#define DP_AUDIO_DELAY1 0x113
> +#define DP_AUDIO_DELAY2 0x114
> +
> #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
>
> +#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
> +# define DP_PWR_NOT_NEEDED (1 << 0)
> +
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> # define DP_PSR_ENABLE (1 << 0)
> # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
Some cosmetic comments.
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/4] drm/dp: add DPCD definitions from eDP 1.2
2015-02-25 12:46 [PATCH 1/4] drm/dp: indentation and ordering cleanups Jani Nikula
2015-02-25 12:46 ` [PATCH 2/4] drm/dp: add DPCD definitions from DP 1.2a Jani Nikula
@ 2015-02-25 12:46 ` Jani Nikula
2015-02-26 9:51 ` sonika
2015-02-25 12:46 ` [PATCH 4/4] drm/dp: add DPCD definitions from eDP 1.4 Jani Nikula
2015-02-26 9:51 ` [PATCH 1/4] drm/dp: indentation and ordering cleanups sonika
3 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2015-02-25 12:46 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx
Mostly display control related DPCD addresses.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 209c5b91b0e8..cc96024e8776 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -426,6 +426,38 @@
#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
+#define DP_EDP_GENERAL_CAP_1 0x701
+
+#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
+
+#define DP_EDP_GENERAL_CAP_2 0x703
+
+#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
+
+#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
+
+#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
+#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
+
+#define DP_EDP_PWMGEN_BIT_COUNT 0x724
+#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
+#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
+
+#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
+
+#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
+
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
+
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
+
+#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
+#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
+
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
--
2.1.4
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] drm/dp: add DPCD definitions from eDP 1.2
2015-02-25 12:46 ` [PATCH 3/4] drm/dp: add DPCD definitions from eDP 1.2 Jani Nikula
@ 2015-02-26 9:51 ` sonika
2015-02-26 13:23 ` [Intel-gfx] " Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: sonika @ 2015-02-26 9:51 UTC (permalink / raw)
To: Jani Nikula, dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
> Mostly display control related DPCD addresses.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/drm/drm_dp_helper.h | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 209c5b91b0e8..cc96024e8776 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -426,6 +426,38 @@
>
> #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
>
> +#define DP_EDP_GENERAL_CAP_1 0x701
> +
> +#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
> +
> +#define DP_EDP_GENERAL_CAP_2 0x703
> +
> +#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
> +
> +#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
> +
> +#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
> +#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
> +
> +#define DP_EDP_PWMGEN_BIT_COUNT 0x724
> +#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
> +#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
> +
> +#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
> +
> +#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
> +
> +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
> +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
> +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
> +
> +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
> +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
> +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
> +
> +#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
> +#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
> +
> #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
> #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
> #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
Checked against edp1.3 spec.
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/dp: add DPCD definitions from eDP 1.2
2015-02-26 9:51 ` sonika
@ 2015-02-26 13:23 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2015-02-26 13:23 UTC (permalink / raw)
To: sonika
Cc: Jani Nikula, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
On Thu, Feb 26, 2015 at 03:21:13PM +0530, sonika wrote:
>
> On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
> >Mostly display control related DPCD addresses.
> >
> >Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >---
> > include/drm/drm_dp_helper.h | 32 ++++++++++++++++++++++++++++++++
> > 1 file changed, 32 insertions(+)
> >
> >diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> >index 209c5b91b0e8..cc96024e8776 100644
> >--- a/include/drm/drm_dp_helper.h
> >+++ b/include/drm/drm_dp_helper.h
> >@@ -426,6 +426,38 @@
> > #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
> >+#define DP_EDP_GENERAL_CAP_1 0x701
> >+
> >+#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
> >+
> >+#define DP_EDP_GENERAL_CAP_2 0x703
> >+
> >+#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
> >+
> >+#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
> >+
> >+#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
> >+#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
> >+
> >+#define DP_EDP_PWMGEN_BIT_COUNT 0x724
> >+#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
> >+#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
> >+
> >+#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
> >+
> >+#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
> >+
> >+#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
> >+#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
> >+#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
> >+
> >+#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
> >+#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
> >+#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
> >+
> >+#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
> >+#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
> >+
> > #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
> > #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
> > #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
> Checked against edp1.3 spec.
>
> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Merged this and patch 1 to drm-misc.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/4] drm/dp: add DPCD definitions from eDP 1.4
2015-02-25 12:46 [PATCH 1/4] drm/dp: indentation and ordering cleanups Jani Nikula
2015-02-25 12:46 ` [PATCH 2/4] drm/dp: add DPCD definitions from DP 1.2a Jani Nikula
2015-02-25 12:46 ` [PATCH 3/4] drm/dp: add DPCD definitions from eDP 1.2 Jani Nikula
@ 2015-02-25 12:46 ` Jani Nikula
2015-02-26 11:58 ` sonika
2015-02-27 19:47 ` [PATCH 4/4] " shuang.he
2015-02-26 9:51 ` [PATCH 1/4] drm/dp: indentation and ordering cleanups sonika
3 siblings, 2 replies; 17+ messages in thread
From: Jani Nikula @ 2015-02-25 12:46 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index cc96024e8776..07d94faa9255 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -168,10 +168,18 @@
#define DP_AUD_DEL_INS2 0x02d
/* End of AV_SYNC_DATA_BLOCK */
+#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
+# define DP_ALPM_CAP (1 << 0)
+
+#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
+# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
+
#define DP_GUID 0x030 /* 1.2 */
#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
# define DP_PSR_IS_SUPPORTED 1
+# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
+
#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
# define DP_PSR_NO_TRAIN_ON_EXIT 1
# define DP_PSR_SETUP_TIME_330 (0 << 1)
@@ -211,6 +219,7 @@
/* link configuration */
#define DP_LINK_BW_SET 0x100
+# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
# define DP_LINK_BW_1_62 0x06
# define DP_LINK_BW_2_7 0x0a
# define DP_LINK_BW_5_4 0x14 /* 1.2 */
@@ -309,15 +318,30 @@
#define DP_AUDIO_DELAY2 0x114
#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
+# define DP_LINK_RATE_SET_SHIFT 0
+# define DP_LINK_RATE_SET_MASK (7 << 0)
+
+#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
+# define DP_ALPM_ENABLE (1 << 0)
+# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
+
+#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
+# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
+# define DP_IRQ_HPD_ENABLE (1 << 1)
#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
# define DP_PWR_NOT_NEEDED (1 << 0)
+#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
+# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
+
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE (1 << 0)
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
# define DP_PSR_CRC_VERIFICATION (1 << 2)
# define DP_PSR_FRAME_CAPTURE (1 << 3)
+# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
+# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
#define DP_ADAPTER_CTRL 0x1a0
# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
@@ -425,6 +449,10 @@
# define DP_SET_POWER_MASK 0x3
#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
+# define DP_EDP_11 0x00
+# define DP_EDP_12 0x01
+# define DP_EDP_13 0x02
+# define DP_EDP_14 0x03
#define DP_EDP_GENERAL_CAP_1 0x701
@@ -432,6 +460,8 @@
#define DP_EDP_GENERAL_CAP_2 0x703
+#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
+
#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
@@ -458,6 +488,9 @@
#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
+#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
+#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
+
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
@@ -476,6 +509,7 @@
#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
# define DP_PSR_LINK_CRC_ERROR (1 << 0)
# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
+# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
# define DP_PSR_CAPS_CHANGE (1 << 0)
@@ -489,6 +523,9 @@
# define DP_PSR_SINK_INTERNAL_ERROR 7
# define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
+# define DP_ALPM_LOCK_TIMEOUT_ERROR_STATUS (1 << 0)
+
/* DP 1.2 Sideband message defines */
/* peer device type - DP 1.2a Table 2-92 */
#define DP_PEER_DEVICE_NONE 0x0
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] drm/dp: add DPCD definitions from eDP 1.4
2015-02-25 12:46 ` [PATCH 4/4] drm/dp: add DPCD definitions from eDP 1.4 Jani Nikula
@ 2015-02-26 11:58 ` sonika
2015-02-26 12:37 ` Jani Nikula
2015-02-27 19:47 ` [PATCH 4/4] " shuang.he
1 sibling, 1 reply; 17+ messages in thread
From: sonika @ 2015-02-26 11:58 UTC (permalink / raw)
To: Jani Nikula, dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/drm/drm_dp_helper.h | 37 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index cc96024e8776..07d94faa9255 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -168,10 +168,18 @@
> #define DP_AUD_DEL_INS2 0x02d
> /* End of AV_SYNC_DATA_BLOCK */
>
> +#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
> +# define DP_ALPM_CAP (1 << 0)
Yes, it is named ALPM_CAP in spec, but to me something like
DP_ALPM_SUPPORTED makes more sense to me here.
> +
> +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
> +# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
Same comment as above.
> +
> #define DP_GUID 0x030 /* 1.2 */
>
> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> # define DP_PSR_IS_SUPPORTED 1
> +# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
> +
> #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
> # define DP_PSR_NO_TRAIN_ON_EXIT 1
> # define DP_PSR_SETUP_TIME_330 (0 << 1)
> @@ -211,6 +219,7 @@
>
> /* link configuration */
> #define DP_LINK_BW_SET 0x100
> +# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> # define DP_LINK_BW_1_62 0x06
> # define DP_LINK_BW_2_7 0x0a
> # define DP_LINK_BW_5_4 0x14 /* 1.2 */
> @@ -309,15 +318,30 @@
> #define DP_AUDIO_DELAY2 0x114
>
> #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
> +# define DP_LINK_RATE_SET_SHIFT 0
> +# define DP_LINK_RATE_SET_MASK (7 << 0)
> +
> +#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
> +# define DP_ALPM_ENABLE (1 << 0)
> +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
> +
> +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
> +# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
> +# define DP_IRQ_HPD_ENABLE (1 << 1)
>
> #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
> # define DP_PWR_NOT_NEEDED (1 << 0)
>
> +#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
> +# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
> +
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> # define DP_PSR_ENABLE (1 << 0)
> # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
> # define DP_PSR_CRC_VERIFICATION (1 << 2)
> # define DP_PSR_FRAME_CAPTURE (1 << 3)
> +# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
> +# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
>
> #define DP_ADAPTER_CTRL 0x1a0
> # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
> @@ -425,6 +449,10 @@
> # define DP_SET_POWER_MASK 0x3
>
> #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
> +# define DP_EDP_11 0x00
> +# define DP_EDP_12 0x01
> +# define DP_EDP_13 0x02
> +# define DP_EDP_14 0x03
>
> #define DP_EDP_GENERAL_CAP_1 0x701
>
> @@ -432,6 +460,8 @@
>
> #define DP_EDP_GENERAL_CAP_2 0x703
>
> +#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
> +
> #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
>
> #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
> @@ -458,6 +488,9 @@
> #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
> #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
>
> +#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
> +#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
> +
> #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
> #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
> #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
> @@ -476,6 +509,7 @@
> #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
> # define DP_PSR_LINK_CRC_ERROR (1 << 0)
> # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
> +# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
>
> #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
> # define DP_PSR_CAPS_CHANGE (1 << 0)
> @@ -489,6 +523,9 @@
> # define DP_PSR_SINK_INTERNAL_ERROR 7
> # define DP_PSR_SINK_STATE_MASK 0x07
>
> +#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
> +# define DP_ALPM_LOCK_TIMEOUT_ERROR_STATUS (1 << 0)
> +
Probably just DP_ALPM_LOCK_TIMEOUT_ERROR ?
> /* DP 1.2 Sideband message defines */
> /* peer device type - DP 1.2a Table 2-92 */
> #define DP_PEER_DEVICE_NONE 0x0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] drm/dp: add DPCD definitions from eDP 1.4
2015-02-26 11:58 ` sonika
@ 2015-02-26 12:37 ` Jani Nikula
2015-02-27 11:10 ` [PATCH v2] drm/dp: add DPCD definitions from DP 1.1 and 1.2a Jani Nikula
2015-02-27 11:11 ` [PATCH v2] drm/dp: add DPCD definitions from eDP 1.4 Jani Nikula
0 siblings, 2 replies; 17+ messages in thread
From: Jani Nikula @ 2015-02-26 12:37 UTC (permalink / raw)
To: sonika, dri-devel@lists.freedesktop.org; +Cc: intel-gfx@lists.freedesktop.org
On Thu, 26 Feb 2015, sonika <sonika.jindal@intel.com> wrote:
> On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> include/drm/drm_dp_helper.h | 37 +++++++++++++++++++++++++++++++++++++
>> 1 file changed, 37 insertions(+)
>>
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index cc96024e8776..07d94faa9255 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -168,10 +168,18 @@
>> #define DP_AUD_DEL_INS2 0x02d
>> /* End of AV_SYNC_DATA_BLOCK */
>>
>> +#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
>> +# define DP_ALPM_CAP (1 << 0)
> Yes, it is named ALPM_CAP in spec, but to me something like
> DP_ALPM_SUPPORTED makes more sense to me here.
I would prefer to keep the same name as in the spec. In many places in
the DPCD, _CAP refers to a capability, so I don't find it confusing.
>> +
>> +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
>> +# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
> Same comment as above.
Likewise. :)
>> +
>> #define DP_GUID 0x030 /* 1.2 */
>>
>> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
>> # define DP_PSR_IS_SUPPORTED 1
>> +# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
>> +
>> #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
>> # define DP_PSR_NO_TRAIN_ON_EXIT 1
>> # define DP_PSR_SETUP_TIME_330 (0 << 1)
>> @@ -211,6 +219,7 @@
>>
>> /* link configuration */
>> #define DP_LINK_BW_SET 0x100
>> +# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
>> # define DP_LINK_BW_1_62 0x06
>> # define DP_LINK_BW_2_7 0x0a
>> # define DP_LINK_BW_5_4 0x14 /* 1.2 */
>> @@ -309,15 +318,30 @@
>> #define DP_AUDIO_DELAY2 0x114
>>
>> #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
>> +# define DP_LINK_RATE_SET_SHIFT 0
>> +# define DP_LINK_RATE_SET_MASK (7 << 0)
>> +
>> +#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
>> +# define DP_ALPM_ENABLE (1 << 0)
>> +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
>> +
>> +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
>> +# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
>> +# define DP_IRQ_HPD_ENABLE (1 << 1)
>>
>> #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
>> # define DP_PWR_NOT_NEEDED (1 << 0)
>>
>> +#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
>> +# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
>> +
>> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
>> # define DP_PSR_ENABLE (1 << 0)
>> # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
>> # define DP_PSR_CRC_VERIFICATION (1 << 2)
>> # define DP_PSR_FRAME_CAPTURE (1 << 3)
>> +# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
>> +# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
>>
>> #define DP_ADAPTER_CTRL 0x1a0
>> # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
>> @@ -425,6 +449,10 @@
>> # define DP_SET_POWER_MASK 0x3
>>
>> #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
>> +# define DP_EDP_11 0x00
>> +# define DP_EDP_12 0x01
>> +# define DP_EDP_13 0x02
>> +# define DP_EDP_14 0x03
>>
>> #define DP_EDP_GENERAL_CAP_1 0x701
>>
>> @@ -432,6 +460,8 @@
>>
>> #define DP_EDP_GENERAL_CAP_2 0x703
>>
>> +#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
>> +
>> #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
>>
>> #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
>> @@ -458,6 +488,9 @@
>> #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
>> #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
>>
>> +#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
>> +#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
>> +
>> #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
>> #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
>> #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
>> @@ -476,6 +509,7 @@
>> #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
>> # define DP_PSR_LINK_CRC_ERROR (1 << 0)
>> # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
>> +# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
>>
>> #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
>> # define DP_PSR_CAPS_CHANGE (1 << 0)
>> @@ -489,6 +523,9 @@
>> # define DP_PSR_SINK_INTERNAL_ERROR 7
>> # define DP_PSR_SINK_STATE_MASK 0x07
>>
>> +#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
>> +# define DP_ALPM_LOCK_TIMEOUT_ERROR_STATUS (1 << 0)
>> +
> Probably just DP_ALPM_LOCK_TIMEOUT_ERROR ?
Agreed.
>> /* DP 1.2 Sideband message defines */
>> /* peer device type - DP 1.2a Table 2-92 */
>> #define DP_PEER_DEVICE_NONE 0x0
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2] drm/dp: add DPCD definitions from DP 1.1 and 1.2a
2015-02-26 12:37 ` Jani Nikula
@ 2015-02-27 11:10 ` Jani Nikula
2015-02-27 11:12 ` Jani Nikula
2015-03-03 2:18 ` shuang.he
2015-02-27 11:11 ` [PATCH v2] drm/dp: add DPCD definitions from eDP 1.4 Jani Nikula
1 sibling, 2 replies; 17+ messages in thread
From: Jani Nikula @ 2015-02-27 11:10 UTC (permalink / raw)
To: Jani Nikula, sonika, dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Add a number of DPCD definitions from DP 1.1 and 1.2a.
v2: drop wrong DP version reference, rename DP training set macros
(Sonika).
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 93 ++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 88 insertions(+), 5 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index a3ecaa06c9db..319d5edfb3b5 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -92,6 +92,15 @@
# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
# define DP_OUI_SUPPORT (1 << 7)
+#define DP_RECEIVE_PORT_0_CAP_0 0x008
+# define DP_LOCAL_EDID_PRESENT (1 << 1)
+# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
+
+#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
+
+#define DP_RECEIVE_PORT_1_CAP_0 0x00a
+#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
+
#define DP_I2C_SPEED_CAP 0x00c /* DPI */
# define DP_I2C_SPEED_1K 0x01
# define DP_I2C_SPEED_5K 0x02
@@ -101,10 +110,16 @@
# define DP_I2C_SPEED_1M 0x20
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
+# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
+# define DP_FRAMING_CHANGE_CAP (1 << 1)
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
+#define DP_ADAPTER_CAP 0x00f /* 1.2 */
+# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
+# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
+
#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
@@ -115,6 +130,44 @@
#define DP_MSTM_CAP 0x021 /* 1.2 */
# define DP_MST_CAP (1 << 0)
+#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
+
+/* AV_SYNC_DATA_BLOCK 1.2 */
+#define DP_AV_GRANULARITY 0x023
+# define DP_AG_FACTOR_MASK (0xf << 0)
+# define DP_AG_FACTOR_3MS (0 << 0)
+# define DP_AG_FACTOR_2MS (1 << 0)
+# define DP_AG_FACTOR_1MS (2 << 0)
+# define DP_AG_FACTOR_500US (3 << 0)
+# define DP_AG_FACTOR_200US (4 << 0)
+# define DP_AG_FACTOR_100US (5 << 0)
+# define DP_AG_FACTOR_10US (6 << 0)
+# define DP_AG_FACTOR_1US (7 << 0)
+# define DP_VG_FACTOR_MASK (0xf << 4)
+# define DP_VG_FACTOR_3MS (0 << 4)
+# define DP_VG_FACTOR_2MS (1 << 4)
+# define DP_VG_FACTOR_1MS (2 << 4)
+# define DP_VG_FACTOR_500US (3 << 4)
+# define DP_VG_FACTOR_200US (4 << 4)
+# define DP_VG_FACTOR_100US (5 << 4)
+
+#define DP_AUD_DEC_LAT0 0x024
+#define DP_AUD_DEC_LAT1 0x025
+
+#define DP_AUD_PP_LAT0 0x026
+#define DP_AUD_PP_LAT1 0x027
+
+#define DP_VID_INTER_LAT 0x028
+
+#define DP_VID_PROG_LAT 0x029
+
+#define DP_REP_LAT 0x02a
+
+#define DP_AUD_DEL_INS0 0x02b
+#define DP_AUD_DEL_INS1 0x02c
+#define DP_AUD_DEL_INS2 0x02d
+/* End of AV_SYNC_DATA_BLOCK */
+
#define DP_GUID 0x030 /* 1.2 */
#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
@@ -173,11 +226,12 @@
# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
# define DP_TRAINING_PATTERN_MASK 0x3
-# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
-# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
-# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
-# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
-# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
+/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
+# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
+# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
+# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
+# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
+# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
@@ -220,14 +274,43 @@
/* bitmask as for DP_I2C_SPEED_CAP */
#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
+# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
+# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
+# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
+
+#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
+#define DP_LINK_QUAL_LANE1_SET 0x10c
+#define DP_LINK_QUAL_LANE2_SET 0x10d
+#define DP_LINK_QUAL_LANE3_SET 0x10e
+# define DP_LINK_QUAL_PATTERN_DISABLE 0
+# define DP_LINK_QUAL_PATTERN_D10_2 1
+# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
+# define DP_LINK_QUAL_PATTERN_PRBS7 3
+# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
+# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
+# define DP_LINK_QUAL_PATTERN_MASK 7
+
+#define DP_TRAINING_LANE0_1_SET2 0x10f
+#define DP_TRAINING_LANE2_3_SET2 0x110
+# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
+# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
+# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
+# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
#define DP_MSTM_CTRL 0x111 /* 1.2 */
# define DP_MST_EN (1 << 0)
# define DP_UP_REQ_EN (1 << 1)
# define DP_UPSTREAM_IS_SRC (1 << 2)
+#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
+#define DP_AUDIO_DELAY1 0x113
+#define DP_AUDIO_DELAY2 0x114
+
#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
+#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
+# define DP_PWR_NOT_NEEDED (1 << 0)
+
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE (1 << 0)
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/dp: add DPCD definitions from DP 1.1 and 1.2a
2015-02-27 11:10 ` [PATCH v2] drm/dp: add DPCD definitions from DP 1.1 and 1.2a Jani Nikula
@ 2015-02-27 11:12 ` Jani Nikula
2015-02-27 13:10 ` Daniel Vetter
2015-03-03 2:18 ` shuang.he
1 sibling, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2015-02-27 11:12 UTC (permalink / raw)
To: sonika, dri-devel@lists.freedesktop.org; +Cc: intel-gfx@lists.freedesktop.org
Apologies, this was supposed to be in reply to
http://mid.gmane.org/54EEECC9.4010902@intel.com
On Fri, 27 Feb 2015, Jani Nikula <jani.nikula@intel.com> wrote:
> Add a number of DPCD definitions from DP 1.1 and 1.2a.
>
> v2: drop wrong DP version reference, rename DP training set macros
> (Sonika).
>
> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/drm/drm_dp_helper.h | 93 ++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 88 insertions(+), 5 deletions(-)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index a3ecaa06c9db..319d5edfb3b5 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -92,6 +92,15 @@
> # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
> # define DP_OUI_SUPPORT (1 << 7)
>
> +#define DP_RECEIVE_PORT_0_CAP_0 0x008
> +# define DP_LOCAL_EDID_PRESENT (1 << 1)
> +# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
> +
> +#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
> +
> +#define DP_RECEIVE_PORT_1_CAP_0 0x00a
> +#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
> +
> #define DP_I2C_SPEED_CAP 0x00c /* DPI */
> # define DP_I2C_SPEED_1K 0x01
> # define DP_I2C_SPEED_5K 0x02
> @@ -101,10 +110,16 @@
> # define DP_I2C_SPEED_1M 0x20
>
> #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
> +# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
> +# define DP_FRAMING_CHANGE_CAP (1 << 1)
> # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
>
> #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
>
> +#define DP_ADAPTER_CAP 0x00f /* 1.2 */
> +# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
> +# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
> +
> #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
> # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
>
> @@ -115,6 +130,44 @@
> #define DP_MSTM_CAP 0x021 /* 1.2 */
> # define DP_MST_CAP (1 << 0)
>
> +#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
> +
> +/* AV_SYNC_DATA_BLOCK 1.2 */
> +#define DP_AV_GRANULARITY 0x023
> +# define DP_AG_FACTOR_MASK (0xf << 0)
> +# define DP_AG_FACTOR_3MS (0 << 0)
> +# define DP_AG_FACTOR_2MS (1 << 0)
> +# define DP_AG_FACTOR_1MS (2 << 0)
> +# define DP_AG_FACTOR_500US (3 << 0)
> +# define DP_AG_FACTOR_200US (4 << 0)
> +# define DP_AG_FACTOR_100US (5 << 0)
> +# define DP_AG_FACTOR_10US (6 << 0)
> +# define DP_AG_FACTOR_1US (7 << 0)
> +# define DP_VG_FACTOR_MASK (0xf << 4)
> +# define DP_VG_FACTOR_3MS (0 << 4)
> +# define DP_VG_FACTOR_2MS (1 << 4)
> +# define DP_VG_FACTOR_1MS (2 << 4)
> +# define DP_VG_FACTOR_500US (3 << 4)
> +# define DP_VG_FACTOR_200US (4 << 4)
> +# define DP_VG_FACTOR_100US (5 << 4)
> +
> +#define DP_AUD_DEC_LAT0 0x024
> +#define DP_AUD_DEC_LAT1 0x025
> +
> +#define DP_AUD_PP_LAT0 0x026
> +#define DP_AUD_PP_LAT1 0x027
> +
> +#define DP_VID_INTER_LAT 0x028
> +
> +#define DP_VID_PROG_LAT 0x029
> +
> +#define DP_REP_LAT 0x02a
> +
> +#define DP_AUD_DEL_INS0 0x02b
> +#define DP_AUD_DEL_INS1 0x02c
> +#define DP_AUD_DEL_INS2 0x02d
> +/* End of AV_SYNC_DATA_BLOCK */
> +
> #define DP_GUID 0x030 /* 1.2 */
>
> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> @@ -173,11 +226,12 @@
> # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
> # define DP_TRAINING_PATTERN_MASK 0x3
>
> -# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
> -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
> -# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
> -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
> -# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
> +/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
> +# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
> +# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
> +# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
> +# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
> +# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
>
> # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
> # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
> @@ -220,14 +274,43 @@
> /* bitmask as for DP_I2C_SPEED_CAP */
>
> #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
> +# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
> +# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
> +# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
> +
> +#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
> +#define DP_LINK_QUAL_LANE1_SET 0x10c
> +#define DP_LINK_QUAL_LANE2_SET 0x10d
> +#define DP_LINK_QUAL_LANE3_SET 0x10e
> +# define DP_LINK_QUAL_PATTERN_DISABLE 0
> +# define DP_LINK_QUAL_PATTERN_D10_2 1
> +# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
> +# define DP_LINK_QUAL_PATTERN_PRBS7 3
> +# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
> +# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
> +# define DP_LINK_QUAL_PATTERN_MASK 7
> +
> +#define DP_TRAINING_LANE0_1_SET2 0x10f
> +#define DP_TRAINING_LANE2_3_SET2 0x110
> +# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
> +# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
> +# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
> +# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
>
> #define DP_MSTM_CTRL 0x111 /* 1.2 */
> # define DP_MST_EN (1 << 0)
> # define DP_UP_REQ_EN (1 << 1)
> # define DP_UPSTREAM_IS_SRC (1 << 2)
>
> +#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
> +#define DP_AUDIO_DELAY1 0x113
> +#define DP_AUDIO_DELAY2 0x114
> +
> #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
>
> +#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
> +# define DP_PWR_NOT_NEEDED (1 << 0)
> +
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> # define DP_PSR_ENABLE (1 << 0)
> # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
> --
> 2.1.4
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/dp: add DPCD definitions from DP 1.1 and 1.2a
2015-02-27 11:12 ` Jani Nikula
@ 2015-02-27 13:10 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2015-02-27 13:10 UTC (permalink / raw)
To: Jani Nikula
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
On Fri, Feb 27, 2015 at 01:12:46PM +0200, Jani Nikula wrote:
>
> Apologies, this was supposed to be in reply to
> http://mid.gmane.org/54EEECC9.4010902@intel.com
>
>
> On Fri, 27 Feb 2015, Jani Nikula <jani.nikula@intel.com> wrote:
> > Add a number of DPCD definitions from DP 1.1 and 1.2a.
> >
> > v2: drop wrong DP version reference, rename DP training set macros
> > (Sonika).
> >
> > Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Merged to drm-misc, thanks.
-Daniel
> > ---
> > include/drm/drm_dp_helper.h | 93 ++++++++++++++++++++++++++++++++++++++++++---
> > 1 file changed, 88 insertions(+), 5 deletions(-)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index a3ecaa06c9db..319d5edfb3b5 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -92,6 +92,15 @@
> > # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
> > # define DP_OUI_SUPPORT (1 << 7)
> >
> > +#define DP_RECEIVE_PORT_0_CAP_0 0x008
> > +# define DP_LOCAL_EDID_PRESENT (1 << 1)
> > +# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
> > +
> > +#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
> > +
> > +#define DP_RECEIVE_PORT_1_CAP_0 0x00a
> > +#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
> > +
> > #define DP_I2C_SPEED_CAP 0x00c /* DPI */
> > # define DP_I2C_SPEED_1K 0x01
> > # define DP_I2C_SPEED_5K 0x02
> > @@ -101,10 +110,16 @@
> > # define DP_I2C_SPEED_1M 0x20
> >
> > #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
> > +# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
> > +# define DP_FRAMING_CHANGE_CAP (1 << 1)
> > # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
> >
> > #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
> >
> > +#define DP_ADAPTER_CAP 0x00f /* 1.2 */
> > +# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
> > +# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
> > +
> > #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
> > # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
> >
> > @@ -115,6 +130,44 @@
> > #define DP_MSTM_CAP 0x021 /* 1.2 */
> > # define DP_MST_CAP (1 << 0)
> >
> > +#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
> > +
> > +/* AV_SYNC_DATA_BLOCK 1.2 */
> > +#define DP_AV_GRANULARITY 0x023
> > +# define DP_AG_FACTOR_MASK (0xf << 0)
> > +# define DP_AG_FACTOR_3MS (0 << 0)
> > +# define DP_AG_FACTOR_2MS (1 << 0)
> > +# define DP_AG_FACTOR_1MS (2 << 0)
> > +# define DP_AG_FACTOR_500US (3 << 0)
> > +# define DP_AG_FACTOR_200US (4 << 0)
> > +# define DP_AG_FACTOR_100US (5 << 0)
> > +# define DP_AG_FACTOR_10US (6 << 0)
> > +# define DP_AG_FACTOR_1US (7 << 0)
> > +# define DP_VG_FACTOR_MASK (0xf << 4)
> > +# define DP_VG_FACTOR_3MS (0 << 4)
> > +# define DP_VG_FACTOR_2MS (1 << 4)
> > +# define DP_VG_FACTOR_1MS (2 << 4)
> > +# define DP_VG_FACTOR_500US (3 << 4)
> > +# define DP_VG_FACTOR_200US (4 << 4)
> > +# define DP_VG_FACTOR_100US (5 << 4)
> > +
> > +#define DP_AUD_DEC_LAT0 0x024
> > +#define DP_AUD_DEC_LAT1 0x025
> > +
> > +#define DP_AUD_PP_LAT0 0x026
> > +#define DP_AUD_PP_LAT1 0x027
> > +
> > +#define DP_VID_INTER_LAT 0x028
> > +
> > +#define DP_VID_PROG_LAT 0x029
> > +
> > +#define DP_REP_LAT 0x02a
> > +
> > +#define DP_AUD_DEL_INS0 0x02b
> > +#define DP_AUD_DEL_INS1 0x02c
> > +#define DP_AUD_DEL_INS2 0x02d
> > +/* End of AV_SYNC_DATA_BLOCK */
> > +
> > #define DP_GUID 0x030 /* 1.2 */
> >
> > #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> > @@ -173,11 +226,12 @@
> > # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
> > # define DP_TRAINING_PATTERN_MASK 0x3
> >
> > -# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
> > -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
> > -# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
> > -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
> > -# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
> > +/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
> > +# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
> > +# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
> > +# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
> > +# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
> > +# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
> >
> > # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
> > # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
> > @@ -220,14 +274,43 @@
> > /* bitmask as for DP_I2C_SPEED_CAP */
> >
> > #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
> > +# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
> > +# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
> > +# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
> > +
> > +#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
> > +#define DP_LINK_QUAL_LANE1_SET 0x10c
> > +#define DP_LINK_QUAL_LANE2_SET 0x10d
> > +#define DP_LINK_QUAL_LANE3_SET 0x10e
> > +# define DP_LINK_QUAL_PATTERN_DISABLE 0
> > +# define DP_LINK_QUAL_PATTERN_D10_2 1
> > +# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
> > +# define DP_LINK_QUAL_PATTERN_PRBS7 3
> > +# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
> > +# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
> > +# define DP_LINK_QUAL_PATTERN_MASK 7
> > +
> > +#define DP_TRAINING_LANE0_1_SET2 0x10f
> > +#define DP_TRAINING_LANE2_3_SET2 0x110
> > +# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
> > +# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
> > +# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
> > +# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
> >
> > #define DP_MSTM_CTRL 0x111 /* 1.2 */
> > # define DP_MST_EN (1 << 0)
> > # define DP_UP_REQ_EN (1 << 1)
> > # define DP_UPSTREAM_IS_SRC (1 << 2)
> >
> > +#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
> > +#define DP_AUDIO_DELAY1 0x113
> > +#define DP_AUDIO_DELAY2 0x114
> > +
> > #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
> >
> > +#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
> > +# define DP_PWR_NOT_NEEDED (1 << 0)
> > +
> > #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> > # define DP_PSR_ENABLE (1 << 0)
> > # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
> > --
> > 2.1.4
> >
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/dp: add DPCD definitions from DP 1.1 and 1.2a
2015-02-27 11:10 ` [PATCH v2] drm/dp: add DPCD definitions from DP 1.1 and 1.2a Jani Nikula
2015-02-27 11:12 ` Jani Nikula
@ 2015-03-03 2:18 ` shuang.he
1 sibling, 0 replies; 17+ messages in thread
From: shuang.he @ 2015-03-03 2:18 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, jani.nikula
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5849
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -9 278/278 269/278
ILK 308/308 308/308
SNB -1 284/284 283/284
IVB 380/380 380/380
BYT 294/294 294/294
HSW -1 387/387 386/387
BDW -1 316/316 315/316
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gem_fence_thrash_bo-write-verify-none PASS(3) FAIL(1)PASS(1)
*PNV igt_gem_fence_thrash_bo-write-verify-x PASS(3) FAIL(1)PASS(1)
*PNV igt_gem_fence_thrash_bo-write-verify-y PASS(3) FAIL(1)PASS(1)
PNV igt_gem_userptr_blits_coherency-sync CRASH(2)PASS(4) CRASH(2)
PNV igt_gem_userptr_blits_coherency-unsync CRASH(2)PASS(3) CRASH(2)
*PNV igt_gem_userptr_blits_minor-normal-sync PASS(2) DMESG_WARN(1)PASS(1)
PNV igt_gen3_render_linear_blits FAIL(3)PASS(3) FAIL(2)
PNV igt_gen3_render_mixed_blits FAIL(2)PASS(6) FAIL(2)
*PNV igt_gem_fence_thrash_bo-write-verify-threaded-none CRASH(1)PASS(3) FAIL(1)CRASH(1)
*SNB igt_gem_fenced_exec_thrash_no-spare-fences-interruptible PASS(1) DMESG_WARN(1)PASS(1)
*HSW igt_gem_storedw_loop_blt PASS(3) DMESG_WARN(1)PASS(1)
*BDW igt_gem_gtt_hog PASS(7) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2] drm/dp: add DPCD definitions from eDP 1.4
2015-02-26 12:37 ` Jani Nikula
2015-02-27 11:10 ` [PATCH v2] drm/dp: add DPCD definitions from DP 1.1 and 1.2a Jani Nikula
@ 2015-02-27 11:11 ` Jani Nikula
2015-02-27 13:46 ` Jindal, Sonika
1 sibling, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2015-02-27 11:11 UTC (permalink / raw)
To: Jani Nikula, sonika, dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Add a number of DPCD definitions from eDP 1.4.
v2: s/DP_ALPM_LOCK_TIMEOUT_ERROR_STATUS/DP_ALPM_LOCK_TIMEOUT_ERROR/
(Sonika)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 319d5edfb3b5..c5fdc2d3ca97 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -168,10 +168,18 @@
#define DP_AUD_DEL_INS2 0x02d
/* End of AV_SYNC_DATA_BLOCK */
+#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
+# define DP_ALPM_CAP (1 << 0)
+
+#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
+# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
+
#define DP_GUID 0x030 /* 1.2 */
#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
# define DP_PSR_IS_SUPPORTED 1
+# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
+
#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
# define DP_PSR_NO_TRAIN_ON_EXIT 1
# define DP_PSR_SETUP_TIME_330 (0 << 1)
@@ -211,6 +219,7 @@
/* link configuration */
#define DP_LINK_BW_SET 0x100
+# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
# define DP_LINK_BW_1_62 0x06
# define DP_LINK_BW_2_7 0x0a
# define DP_LINK_BW_5_4 0x14 /* 1.2 */
@@ -307,15 +316,30 @@
#define DP_AUDIO_DELAY2 0x114
#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
+# define DP_LINK_RATE_SET_SHIFT 0
+# define DP_LINK_RATE_SET_MASK (7 << 0)
+
+#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
+# define DP_ALPM_ENABLE (1 << 0)
+# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
+
+#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
+# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
+# define DP_IRQ_HPD_ENABLE (1 << 1)
#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
# define DP_PWR_NOT_NEEDED (1 << 0)
+#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
+# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
+
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE (1 << 0)
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
# define DP_PSR_CRC_VERIFICATION (1 << 2)
# define DP_PSR_FRAME_CAPTURE (1 << 3)
+# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
+# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
#define DP_ADAPTER_CTRL 0x1a0
# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
@@ -423,6 +447,10 @@
# define DP_SET_POWER_MASK 0x3
#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
+# define DP_EDP_11 0x00
+# define DP_EDP_12 0x01
+# define DP_EDP_13 0x02
+# define DP_EDP_14 0x03
#define DP_EDP_GENERAL_CAP_1 0x701
@@ -430,6 +458,8 @@
#define DP_EDP_GENERAL_CAP_2 0x703
+#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
+
#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
@@ -456,6 +486,9 @@
#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
+#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
+#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
+
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
@@ -474,6 +507,7 @@
#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
# define DP_PSR_LINK_CRC_ERROR (1 << 0)
# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
+# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
# define DP_PSR_CAPS_CHANGE (1 << 0)
@@ -487,6 +521,9 @@
# define DP_PSR_SINK_INTERNAL_ERROR 7
# define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
+# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
+
/* DP 1.2 Sideband message defines */
/* peer device type - DP 1.2a Table 2-92 */
#define DP_PEER_DEVICE_NONE 0x0
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/dp: add DPCD definitions from eDP 1.4
2015-02-27 11:11 ` [PATCH v2] drm/dp: add DPCD definitions from eDP 1.4 Jani Nikula
@ 2015-02-27 13:46 ` Jindal, Sonika
0 siblings, 0 replies; 17+ messages in thread
From: Jindal, Sonika @ 2015-02-27 13:46 UTC (permalink / raw)
To: Jani Nikula, dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
On 2/27/2015 4:41 PM, Jani Nikula wrote:
> Add a number of DPCD definitions from eDP 1.4.
>
> v2: s/DP_ALPM_LOCK_TIMEOUT_ERROR_STATUS/DP_ALPM_LOCK_TIMEOUT_ERROR/
> (Sonika)
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/drm/drm_dp_helper.h | 37 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 319d5edfb3b5..c5fdc2d3ca97 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -168,10 +168,18 @@
> #define DP_AUD_DEL_INS2 0x02d
> /* End of AV_SYNC_DATA_BLOCK */
>
> +#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
> +# define DP_ALPM_CAP (1 << 0)
> +
> +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
> +# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
> +
> #define DP_GUID 0x030 /* 1.2 */
>
> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> # define DP_PSR_IS_SUPPORTED 1
> +# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
> +
> #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
> # define DP_PSR_NO_TRAIN_ON_EXIT 1
> # define DP_PSR_SETUP_TIME_330 (0 << 1)
> @@ -211,6 +219,7 @@
>
> /* link configuration */
> #define DP_LINK_BW_SET 0x100
> +# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> # define DP_LINK_BW_1_62 0x06
> # define DP_LINK_BW_2_7 0x0a
> # define DP_LINK_BW_5_4 0x14 /* 1.2 */
> @@ -307,15 +316,30 @@
> #define DP_AUDIO_DELAY2 0x114
>
> #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
> +# define DP_LINK_RATE_SET_SHIFT 0
> +# define DP_LINK_RATE_SET_MASK (7 << 0)
> +
> +#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
> +# define DP_ALPM_ENABLE (1 << 0)
> +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
> +
> +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
> +# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
> +# define DP_IRQ_HPD_ENABLE (1 << 1)
>
> #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
> # define DP_PWR_NOT_NEEDED (1 << 0)
>
> +#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
> +# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
> +
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> # define DP_PSR_ENABLE (1 << 0)
> # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
> # define DP_PSR_CRC_VERIFICATION (1 << 2)
> # define DP_PSR_FRAME_CAPTURE (1 << 3)
> +# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
> +# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
>
> #define DP_ADAPTER_CTRL 0x1a0
> # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
> @@ -423,6 +447,10 @@
> # define DP_SET_POWER_MASK 0x3
>
> #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
> +# define DP_EDP_11 0x00
> +# define DP_EDP_12 0x01
> +# define DP_EDP_13 0x02
> +# define DP_EDP_14 0x03
>
> #define DP_EDP_GENERAL_CAP_1 0x701
>
> @@ -430,6 +458,8 @@
>
> #define DP_EDP_GENERAL_CAP_2 0x703
>
> +#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
> +
> #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
>
> #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
> @@ -456,6 +486,9 @@
> #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
> #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
>
> +#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
> +#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
> +
> #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
> #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
> #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
> @@ -474,6 +507,7 @@
> #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
> # define DP_PSR_LINK_CRC_ERROR (1 << 0)
> # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
> +# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
>
> #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
> # define DP_PSR_CAPS_CHANGE (1 << 0)
> @@ -487,6 +521,9 @@
> # define DP_PSR_SINK_INTERNAL_ERROR 7
> # define DP_PSR_SINK_STATE_MASK 0x07
>
> +#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
> +# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
> +
> /* DP 1.2 Sideband message defines */
> /* peer device type - DP 1.2a Table 2-92 */
> #define DP_PEER_DEVICE_NONE 0x0
>
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] drm/dp: add DPCD definitions from eDP 1.4
2015-02-25 12:46 ` [PATCH 4/4] drm/dp: add DPCD definitions from eDP 1.4 Jani Nikula
2015-02-26 11:58 ` sonika
@ 2015-02-27 19:47 ` shuang.he
1 sibling, 0 replies; 17+ messages in thread
From: shuang.he @ 2015-02-27 19:47 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, jani.nikula
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5825
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 282/282 282/282
ILK 308/308 308/308
SNB 326/326 326/326
IVB 379/379 379/379
BYT 294/294 294/294
HSW -1 387/387 386/387
BDW -1 316/316 315/316
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*HSW igt_gem_storedw_loop_bsd PASS(1) DMESG_WARN(1)PASS(1)
*BDW igt_gem_gtt_hog PASS(3) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] drm/dp: indentation and ordering cleanups
2015-02-25 12:46 [PATCH 1/4] drm/dp: indentation and ordering cleanups Jani Nikula
` (2 preceding siblings ...)
2015-02-25 12:46 ` [PATCH 4/4] drm/dp: add DPCD definitions from eDP 1.4 Jani Nikula
@ 2015-02-26 9:51 ` sonika
3 siblings, 0 replies; 17+ messages in thread
From: sonika @ 2015-02-26 9:51 UTC (permalink / raw)
To: Jani Nikula, dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
> Keep the DPCD macros ordered by address, and make indentation conform to
> the rest of the file.
>
> commit e045d20bef41707dbba676e58624b54f9f39e172
> Author: Sonika Jindal <sonika.jindal@intel.com>
> Date: Thu Feb 19 13:16:44 2015 +0530
>
> drm: Adding edp1.4 specific dpcd macros
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> ---
>
> Daniel, this might be squashed into the above commit in the drm-misc
> tree.
> ---
> include/drm/drm_dp_helper.h | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index d4803224028f..98fefe45d158 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -92,9 +92,6 @@
> # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
> # define DP_OUI_SUPPORT (1 << 7)
>
> -#define DP_SUPPORTED_LINK_RATES 0x010 /*eDP 1.4*/
> -#define DP_MAX_SUPPORTED_RATES 0x8
> -
> #define DP_I2C_SPEED_CAP 0x00c /* DPI */
> # define DP_I2C_SPEED_1K 0x01
> # define DP_I2C_SPEED_5K 0x02
> @@ -105,8 +102,12 @@
>
> #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
> # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
> +
> #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
>
> +#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
> +# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
> +
> /* Multiple stream transport */
> #define DP_FAUX_CAP 0x020 /* 1.2 */
> # define DP_FAUX_CAP_1 (1 << 0)
> @@ -225,7 +226,7 @@
> # define DP_UP_REQ_EN (1 << 1)
> # define DP_UPSTREAM_IS_SRC (1 << 2)
>
> -#define DP_LINK_RATE_SET 0x115
> +#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
>
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> # define DP_PSR_ENABLE (1 << 0)
> @@ -338,7 +339,7 @@
> # define DP_SET_POWER_D3 0x2
> # define DP_SET_POWER_MASK 0x3
>
> -#define DP_EDP_DPCD_REV 0x700
> +#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
>
> #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
> #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread