Re: [PATCH V7 1/3] MIPS: Rearrange PTE bits into fixed positions.

[David Daney <ddaney.cavm@gmail.com>]

On 02/26/2015 04:16 PM, Steven J. Hill wrote:
> From: "Steven J. Hill" <Steven.Hill@imgtec.com>
>
> This patch rearranges the PTE bits into fixed positions for R2
> and later cores. In the past, the TLB handling code did runtime
> checking of RI/XI and adjusted the shifts and rotates in order
> to fit the largest PFN value into the PTE. The checking now
> occurs when building the TLB handler, thus eliminating those
> checks. These new arrangements also define the largest possible
> PFN value that can fit in the PTE. HUGE page support is only
> available for 64-bit cores. Layouts of the PTE bits are now:
>
>     64-bit, R1 or earlier:     CCC D V G [S H] M A W R P
>     32-bit, R1 or earler:      CCC D V G M A W R P
>     64-bit, R2 or later:       CCC D V G RI/R XI [S H] M A W P
>     32-bit, R2 or later:       CCC D V G RI/R XI M A W P
>

That's not really what I meant in my previous response on the subject.
When I said:

     Why not just use RI for everything, instead of taking up two bits
     to represent a single binary concept?

     For the case where there is no RI hardware active, it is a purely
     software bit and you can easily invert the meaning and just have a
     _PAGE_NO_READ bit.

I envisioned something like:

     64-bit, all revisions:    CCC D V G RI XI [S H] M A W P
     32-bit, all revisions:    CCC D V G RI XI M A W P

Are there enough bits to include XI even if hardware doens't support XI?

David Daney