[Question] How can we support outer shareable on ARM64?

[thunder.leizhen@huawei.com (leizhen)]

Hi,

Now, both cacheable memory shareability attribute and barrier are fixed to inner shareable. But
I afraid some hardware need outer shareable. If hardware support both inner and outer, do we need
to optimize?

for example(the code for now):
#define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
#define smp_mb()	dmb(ish)

How can we support both inner and outer shareable, or selectable?

Thanks
Zhen Lei