From mboxrd@z Thu Jan 1 00:00:00 1970 From: sudeep.holla@arm.com (Sudeep Holla) Date: Tue, 03 Mar 2015 16:00:12 +0000 Subject: [PATCH v2 0/5] arm-cci400: PMU monitoring support on ARM64 In-Reply-To: <1425295754-13376-1-git-send-email-suzuki.poulose@arm.com> References: <1425295754-13376-1-git-send-email-suzuki.poulose@arm.com> Message-ID: <54F5DA8C.7080609@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 02/03/15 11:29, Suzuki K. Poulose wrote: > From: "Suzuki K. Poulose" > > This series enables the PMU monitoring support for CCI400 on ARM64. > The existing CCI400 driver code is a mix of PMU driver and the MCPM > driver code. The MCPM driver is only used on ARM(32) and contains > arm32 assembly and hence can't be built on ARM64. This patch splits > the code to > > - ARM_CCI400_PORT_CTRL driver - depends on ARM && V7 > - ARM_CCI400_PMU driver > > Accessing the Peripheral ID2 register(PID2) on CCI-400, to detect > the revision of the chipset, is a secure operation. Hence, it prevents > us from running this on non-secure platforms. The issue is overcome by > explicitly mentioning the revision number of the CCI PMU in the device tree > binding. The device-tree binding has been updated with the new bindings. > > i.e, arm-cci-400-pmu,r0 => revision 0 > arm-cci-400-pmu,r1 => revision 1 > arm-cci-400-pmu => (old) DEPRECATED > > The old binding has been DEPRECATED and must be used only on ARM32 > system with secure access. We don't have a reliable dynamic way to detect > if the system is running secure. This series tries to use the best safe > method by relying on the availability of MCPM(as it was prior to the series). > It is upto the MCPM platform driver to decide, if the system is secure before > it goes ahead and registers its drivers and pokes the CCI. This series doesn't > address/solve the problem of MCPM. I will be happy to use a better approach, > if there is any. > > Tested on (non-secure)TC2 and Juno. > For the series: Tested-by: Sudeep Holla (on secure/MCPM TC2) Regards, Sudeep From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sudeep Holla Subject: Re: [PATCH v2 0/5] arm-cci400: PMU monitoring support on ARM64 Date: Tue, 03 Mar 2015 16:00:12 +0000 Message-ID: <54F5DA8C.7080609@arm.com> References: <1425295754-13376-1-git-send-email-suzuki.poulose@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <1425295754-13376-1-git-send-email-suzuki.poulose-5wv7dgnIgG8@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: "Suzuki K. Poulose" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" Cc: Sudeep Holla , "nico-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org" , "b.zolnierkie-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org" , "kgene-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "a.kesavan-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org" , "arnd-r2nGTMty4D4@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Liviu Dudau , Lorenzo Pieralisi , Pawel Moll , "olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org" , Punit Agrawal , Will Deacon , Catalin Marinas List-Id: devicetree@vger.kernel.org On 02/03/15 11:29, Suzuki K. Poulose wrote: > From: "Suzuki K. Poulose" > > This series enables the PMU monitoring support for CCI400 on ARM64. > The existing CCI400 driver code is a mix of PMU driver and the MCPM > driver code. The MCPM driver is only used on ARM(32) and contains > arm32 assembly and hence can't be built on ARM64. This patch splits > the code to > > - ARM_CCI400_PORT_CTRL driver - depends on ARM && V7 > - ARM_CCI400_PMU driver > > Accessing the Peripheral ID2 register(PID2) on CCI-400, to detect > the revision of the chipset, is a secure operation. Hence, it prevents > us from running this on non-secure platforms. The issue is overcome by > explicitly mentioning the revision number of the CCI PMU in the device tree > binding. The device-tree binding has been updated with the new bindings. > > i.e, arm-cci-400-pmu,r0 => revision 0 > arm-cci-400-pmu,r1 => revision 1 > arm-cci-400-pmu => (old) DEPRECATED > > The old binding has been DEPRECATED and must be used only on ARM32 > system with secure access. We don't have a reliable dynamic way to detect > if the system is running secure. This series tries to use the best safe > method by relying on the availability of MCPM(as it was prior to the series). > It is upto the MCPM platform driver to decide, if the system is secure before > it goes ahead and registers its drivers and pokes the CCI. This series doesn't > address/solve the problem of MCPM. I will be happy to use a better approach, > if there is any. > > Tested on (non-secure)TC2 and Juno. > For the series: Tested-by: Sudeep Holla (on secure/MCPM TC2) Regards, Sudeep -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756843AbbCCQAQ (ORCPT ); Tue, 3 Mar 2015 11:00:16 -0500 Received: from service87.mimecast.com ([91.220.42.44]:52917 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756742AbbCCQAN convert rfc822-to-8bit (ORCPT ); Tue, 3 Mar 2015 11:00:13 -0500 Message-ID: <54F5DA8C.7080609@arm.com> Date: Tue, 03 Mar 2015 16:00:12 +0000 From: Sudeep Holla User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: "Suzuki K. Poulose" , "linux-arm-kernel@lists.infradead.org" CC: Sudeep Holla , "nico@linaro.org" , "b.zolnierkie@samsung.com" , "kgene@kernel.org" , "a.kesavan@samsung.com" , "arnd@arndb.de" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Liviu Dudau , Lorenzo Pieralisi , Pawel Moll , "olof@lixom.net" , Punit Agrawal , Will Deacon , Catalin Marinas Subject: Re: [PATCH v2 0/5] arm-cci400: PMU monitoring support on ARM64 References: <1425295754-13376-1-git-send-email-suzuki.poulose@arm.com> In-Reply-To: <1425295754-13376-1-git-send-email-suzuki.poulose@arm.com> X-OriginalArrivalTime: 03 Mar 2015 16:00:09.0940 (UTC) FILETIME=[201F7940:01D055CB] X-MC-Unique: 115030316001116001 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/03/15 11:29, Suzuki K. Poulose wrote: > From: "Suzuki K. Poulose" > > This series enables the PMU monitoring support for CCI400 on ARM64. > The existing CCI400 driver code is a mix of PMU driver and the MCPM > driver code. The MCPM driver is only used on ARM(32) and contains > arm32 assembly and hence can't be built on ARM64. This patch splits > the code to > > - ARM_CCI400_PORT_CTRL driver - depends on ARM && V7 > - ARM_CCI400_PMU driver > > Accessing the Peripheral ID2 register(PID2) on CCI-400, to detect > the revision of the chipset, is a secure operation. Hence, it prevents > us from running this on non-secure platforms. The issue is overcome by > explicitly mentioning the revision number of the CCI PMU in the device tree > binding. The device-tree binding has been updated with the new bindings. > > i.e, arm-cci-400-pmu,r0 => revision 0 > arm-cci-400-pmu,r1 => revision 1 > arm-cci-400-pmu => (old) DEPRECATED > > The old binding has been DEPRECATED and must be used only on ARM32 > system with secure access. We don't have a reliable dynamic way to detect > if the system is running secure. This series tries to use the best safe > method by relying on the availability of MCPM(as it was prior to the series). > It is upto the MCPM platform driver to decide, if the system is secure before > it goes ahead and registers its drivers and pokes the CCI. This series doesn't > address/solve the problem of MCPM. I will be happy to use a better approach, > if there is any. > > Tested on (non-secure)TC2 and Juno. > For the series: Tested-by: Sudeep Holla (on secure/MCPM TC2) Regards, Sudeep