From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v3 13/24] xen/arm: Implement hypercall PHYSDEVOP_{, un}map_pirq Date: Wed, 04 Mar 2015 14:37:35 +0000 Message-ID: <54F718AF.7010104@linaro.org> References: <1421159133-31526-1-git-send-email-julien.grall@linaro.org> <1421159133-31526-14-git-send-email-julien.grall@linaro.org> <54C932BF.5070009@linaro.org> <54CA2709.9080409@linaro.org> <1424451224.30924.357.camel@citrix.com> <54EB4C98.8020107@linaro.org> <1424707341.27930.189.camel@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YTAR6-0007j9-LD for xen-devel@lists.xenproject.org; Wed, 04 Mar 2015 14:38:08 +0000 Received: by wesp10 with SMTP id p10so44569563wes.12 for ; Wed, 04 Mar 2015 06:38:04 -0800 (PST) In-Reply-To: <1424707341.27930.189.camel@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , Jan Beulich Cc: xen-devel@lists.xenproject.org, tim@xen.org, stefano.stabellini@citrix.com, Stefano Stabellini List-Id: xen-devel@lists.xenproject.org Hi, On 23/02/15 16:02, Ian Campbell wrote: > On Mon, 2015-02-23 at 15:51 +0000, Julien Grall wrote: >> On 20/02/15 16:53, Ian Campbell wrote: > >>> Are we absolutely 100% sure that we will never ever want to map hardware >>> IRQs to guests on ARMs using pirq-type event channels? Because that is >>> what we are essentially ruling out here. >> >> That would happen if we decide to implement an interrupt controller >> which doesn't support virtualization. > > Good point. It's pretty unlikely but not absolutely impossible. So we > should avoid reusing the pirq evtchn type for this. Jan suggested > XENDOMCTL_bind_pt_irq which is looking better and better... I looked to the interface of XENDOMCTL_bind_pt_irq and I'm not sure about the meaning of machine_irq and isa_irq. AFAIU the code: machine_irq => guest PIRQ isa_irq => host IRQ am I right? Regards, -- Julien Grall