From mboxrd@z Thu Jan  1 00:00:00 1970
From: Eric Nelson <eric.nelson@boundarydevices.com>
Subject: Re: [RFC PATCH 5/6] ASoC: sgtl5000: disable internal
	PLL early
Date: Fri, 06 Mar 2015 15:16:21 -0700
Message-ID: <54FA2735.9000805@boundarydevices.com>
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To: Mark Brown <broonie@kernel.org>
Cc: fabio.estevam@freescale.com, alsa-devel@alsa-project.org, lars@metafoo.de, tiwai@suse.de, lgirdwood@gmail.com, rmk+kernel@arm.linux.org.uk, jean-michel.hautbois@vodalys.com, troy.kisky@boundarydevices.com
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Hi Mark,

On 03/06/2015 01:15 PM, Mark Brown wrote:
> On Thu, Feb 26, 2015 at 03:54:32PM -0700, Eric Nelson wrote:
> 
>> static const struct reg_default sgtl5000_reg_defaults[] = { {
>> SGTL5000_CHIP_DIG_POWER,		0x0000 }, -	{ SGTL5000_CHIP_CLK_CTRL,
>> 0x0008 },
> 
> Again, you shouldn't be changing the register defaults table unless
> the defaults don't match power up values.
> 

I described the rational in response to patch 2: there's a
dependency on the PLLs being disabled before a write to
ANA_POWER.

Regards,


Eric
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