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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Chris Wilson <chris@chris-wilson.co.uk>,
	Daniel Vetter <daniel@ffwll.ch>,
	"Song, Ruiling" <ruiling.song@intel.com>,
	"Vetter, Daniel" <daniel.vetter@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Yang, Rong R" <rong.r.yang@intel.com>,
	"beignet@lists.freedesktop.org" <beignet@lists.freedesktop.org>,
	"Weinehall, David" <david.weinehall@intel.com>
Subject: Re: Preventing zero GPU virtual address allocation
Date: Mon, 09 Mar 2015 08:46:15 -0700	[thread overview]
Message-ID: <54FDC047.9090202@virtuousgeek.org> (raw)
In-Reply-To: <20150305210702.GC18784@nuc-i3427.alporthouse.com>

On 03/05/2015 01:07 PM, Chris Wilson wrote:
> On Thu, Mar 05, 2015 at 04:27:59PM +0100, Daniel Vetter wrote:
>> I recommended exposing the PIN_BIAS since that will work without full
>> ppgtt too. And yeah for full ppgtt we could just use svm where userspace
>> controls the address, but since that's still a bit out we might need a
>> quick interim solution?
> 
> Letting userspace control the address of bo used in a batch is about 2
> patches each of ~100 lines. And it could be used will full-ppgtt before
> svm if mesa wants to take complete control of its layout. I think it is
> one of those useful tools that is likely to find uses far beyond the
> initial justification.

Well we need someone to pick it up and do it; we've already shafted
userspace for several years due to foot dragging on the command
parser...  I hope something as simple as this doesn't stall out.

Jesse

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  reply	other threads:[~2015-03-09 15:45 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-05  2:56 Preventing zero GPU virtual address allocation Song, Ruiling
2015-03-05 12:52 ` [Intel-gfx] " Daniel Vetter
2015-03-05 13:01   ` Chris Wilson
2015-03-05 15:27     ` [Intel-gfx] " Daniel Vetter
2015-03-05 21:07       ` Chris Wilson
2015-03-09 15:46         ` Jesse Barnes [this message]
2015-03-09 15:49           ` Jesse Barnes
2015-03-06  2:11       ` [Intel-gfx] " Zou, Nanhai
2015-03-06  8:39         ` [Beignet] " Chris Wilson
2015-03-09  2:34           ` Zou, Nanhai
2015-03-09 12:02             ` [Intel-gfx] " Chris Wilson
2015-03-10  1:57               ` Zou, Nanhai
2015-03-13  9:10               ` [Beignet] " David Weinehall
2015-03-13  9:18                 ` [Intel-gfx] " Chris Wilson
2015-03-13  9:27                 ` Daniel Vetter
2015-03-13 16:58                   ` [Beignet] " Chris Wilson
2015-03-13 17:13                     ` [Intel-gfx] " Daniel Vetter
2015-03-13 17:34                       ` [Beignet] " Chris Wilson
2015-03-13 17:49                         ` [Intel-gfx] " Daniel Vetter
2015-03-16  2:29                       ` [Beignet] " Song, Ruiling
2015-03-16  8:52                         ` Daniel Vetter
2015-03-16 20:10                           ` Jesse Barnes
2015-03-17  1:19                             ` [Intel-gfx] " Zhigang Gong
2015-03-17  2:29                             ` Zou, Nanhai
2015-03-17 15:13                               ` [Beignet] " Jesse Barnes
2015-03-19  3:22                                 ` [Intel-gfx] " Song, Ruiling
2015-03-19 10:09                                   ` [Beignet] " David Weinehall
2015-03-19 14:58                                     ` Daniel Vetter
2015-03-20  3:01                                       ` Song, Ruiling
2015-03-17 10:01                             ` Daniel Vetter
2015-03-16 20:11                           ` Jesse Barnes

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