From: Thor Thayer <tthayer@opensource.altera.com>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Mark Brown <broonie@kernel.org>,
Grant Likely <grant.likely@linaro.org>,
Jiri Kosina <jkosina@suse.cz>, Pawel Moll <pawel.moll@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
<ijc+devicetree@hellion.org.uk>, <dinguyen@opensource.altera.com>,
Linux Documentation List <linux-doc@vger.kernel.org>,
<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<tthayer.linux@gmail.com>, Axel Lin <axel.lin@ingics.com>,
<baruch@tkos.co.il>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Jingoo Han <jg1.han@samsung.com>,
Kumar Gala <galak@codeaurora.org>
Subject: Re: [RFC/PATCHv2 2/3] dt-binding: spi: spi-dw: Select 16b or 32b access for Designware SPI
Date: Mon, 9 Mar 2015 13:11:28 -0500 [thread overview]
Message-ID: <54FDE250.3050705@opensource.altera.com> (raw)
In-Reply-To: <CAHp75Vddg3T4oymsixbJWPWnELF3fE5Z4HRe4CxAFd+Eb=VVmA@mail.gmail.com>
On 03/07/2015 01:58 PM, Andy Shevchenko wrote:
> On Sat, Mar 7, 2015 at 1:46 AM, <tthayer@opensource.altera.com> wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Altera's Arria10 architecture requires a 32bit write accesses for
>> APB peripherals. The current spi-dw driver uses 16bit accesses in
>> some locations. This patch updated the bindings with an optional
>> field in the devicetree to select 32bit accesses.
>>
>
> One comment below.
>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>> Documentation/devicetree/bindings/spi/spi-dw.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/spi-dw.txt b/Documentation/devicetree/bindings/spi/spi-dw.txt
>> index 7b63ed6..034dbdd 100644
>> --- a/Documentation/devicetree/bindings/spi/spi-dw.txt
>> +++ b/Documentation/devicetree/bindings/spi/spi-dw.txt
>> @@ -11,6 +11,7 @@ Required properties:
>>
>> Optional properties:
>> - cs-gpios: see spi-bus.txt
>> +- 32bit_access : use 32 bit register accesses
>>
>
> The most big issue for my opinion with DT is an absence of the
> standard for naming properties.
>
> So, why underscore? May be it's a time to append a generic description
> of this field to Documentation/devicetree/…
>
Hi Andy,
I'm use the underscore to make it easier to read but I'm open to
suggestions.
I stay away from dashes because these variable names are problematic to
parse in languages like Python which may be used as an external tool.
I don't mind making it just 32bit if that is preferable or implementing
a better field name.
Thanks for reviewing
WARNING: multiple messages have this Message-ID (diff)
From: Thor Thayer <tthayer@opensource.altera.com>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Mark Brown <broonie@kernel.org>,
Grant Likely <grant.likely@linaro.org>,
Jiri Kosina <jkosina@suse.cz>, Pawel Moll <pawel.moll@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
ijc+devicetree@hellion.org.uk, dinguyen@opensource.altera.com,
Linux Documentation List <linux-doc@vger.kernel.org>,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
tthayer.linux@gmail.com, Axel Lin <axel.lin@ingics.com>,
baruch@tkos.co.il,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Jingoo Han <jg1.han@samsung.com>,
Kumar Gala <galak@codeaurora.org>
Subject: Re: [RFC/PATCHv2 2/3] dt-binding: spi: spi-dw: Select 16b or 32b access for Designware SPI
Date: Mon, 9 Mar 2015 13:11:28 -0500 [thread overview]
Message-ID: <54FDE250.3050705@opensource.altera.com> (raw)
In-Reply-To: <CAHp75Vddg3T4oymsixbJWPWnELF3fE5Z4HRe4CxAFd+Eb=VVmA@mail.gmail.com>
On 03/07/2015 01:58 PM, Andy Shevchenko wrote:
> On Sat, Mar 7, 2015 at 1:46 AM, <tthayer@opensource.altera.com> wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Altera's Arria10 architecture requires a 32bit write accesses for
>> APB peripherals. The current spi-dw driver uses 16bit accesses in
>> some locations. This patch updated the bindings with an optional
>> field in the devicetree to select 32bit accesses.
>>
>
> One comment below.
>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>> Documentation/devicetree/bindings/spi/spi-dw.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/spi-dw.txt b/Documentation/devicetree/bindings/spi/spi-dw.txt
>> index 7b63ed6..034dbdd 100644
>> --- a/Documentation/devicetree/bindings/spi/spi-dw.txt
>> +++ b/Documentation/devicetree/bindings/spi/spi-dw.txt
>> @@ -11,6 +11,7 @@ Required properties:
>>
>> Optional properties:
>> - cs-gpios: see spi-bus.txt
>> +- 32bit_access : use 32 bit register accesses
>>
>
> The most big issue for my opinion with DT is an absence of the
> standard for naming properties.
>
> So, why underscore? May be it's a time to append a generic description
> of this field to Documentation/devicetree/…
>
Hi Andy,
I'm use the underscore to make it easier to read but I'm open to
suggestions.
I stay away from dashes because these variable names are problematic to
parse in languages like Python which may be used as an external tool.
I don't mind making it just 32bit if that is preferable or implementing
a better field name.
Thanks for reviewing
next prev parent reply other threads:[~2015-03-09 18:11 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-06 23:46 [RFC/PATCHv2 0/3] spi: spi-dw: Select 16b or 32b register access tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2015-03-06 23:46 ` tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
[not found] ` <1425685594-26595-1-git-send-email-tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2015-03-06 23:46 ` [RFC/PATCHv2 1/3] spi: dw-spi: Single Register read to clear IRQs tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2015-03-06 23:46 ` tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2015-03-07 19:46 ` Andy Shevchenko
2015-03-09 18:43 ` Mark Brown
2015-03-06 23:46 ` [RFC/PATCHv2 2/3] dt-binding: spi: spi-dw: Select 16b or 32b access for Designware SPI tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2015-03-06 23:46 ` tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2015-03-07 19:58 ` Andy Shevchenko
2015-03-09 18:11 ` Thor Thayer [this message]
2015-03-09 18:11 ` Thor Thayer
[not found] ` <54FDE250.3050705-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2015-03-09 18:19 ` Mark Brown
[not found] ` <20150309181936.GU28806-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2015-03-09 18:25 ` Thor Thayer
2015-03-09 18:25 ` Thor Thayer
2015-03-06 23:46 ` [RFC/PATCHv2 3/3] spi: dw-spi: Pointers select 16b vs. 32b DesignWare access tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2015-03-06 23:46 ` tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
[not found] ` <1425685594-26595-4-git-send-email-tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2015-03-07 19:52 ` Andy Shevchenko
2015-03-09 18:01 ` Thor Thayer
2015-03-09 18:01 ` Thor Thayer
[not found] ` <54FDDFE6.8010109-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2015-03-09 18:54 ` Andy Shevchenko
[not found] ` <CAHp75Vf6dgobzZyJxu8eiqGgC7FRrwLCmyMf5Agk6S3jHDj4bw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-03-09 19:47 ` Thor Thayer
2015-03-09 19:47 ` Thor Thayer
2015-03-09 20:02 ` Andy Shevchenko
[not found] ` <CAHp75VcmNOaiyRNLFzQT7nKS6piZzpYSoS785J86rKtNXx6KNg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-03-10 20:34 ` Thor Thayer
2015-03-10 20:34 ` Thor Thayer
2015-03-10 20:40 ` Mark Brown
[not found] ` <54FF556A.3020408-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2015-03-10 20:44 ` Andy Shevchenko
2015-03-10 22:22 ` Thor Thayer
2015-03-10 22:22 ` Thor Thayer
[not found] ` <54FF6E91.1010704-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2015-03-11 10:27 ` Andy Shevchenko
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