From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YV65a-0000o1-Kj for qemu-devel@nongnu.org; Mon, 09 Mar 2015 18:23:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YV65X-00045H-4X for qemu-devel@nongnu.org; Mon, 09 Mar 2015 18:23:54 -0400 Received: from v220110690675601.yourvserver.net ([37.221.199.173]:35553) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YV65W-000453-RQ for qemu-devel@nongnu.org; Mon, 09 Mar 2015 18:23:51 -0400 Message-ID: <54FE1D68.1050709@weilnetz.de> Date: Mon, 09 Mar 2015 23:23:36 +0100 From: Stefan Weil MIME-Version: 1.0 References: <201503091502.11484.wpaul@windriver.com> In-Reply-To: <201503091502.11484.wpaul@windriver.com> Content-Type: multipart/alternative; boundary="------------080209080801060908090107" Subject: Re: [Qemu-devel] Fix for incorrect SYSRET instruction implementation -- anyone looked at this yet? List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bill Paul , qemu-devel Cc: Paolo Bonzini , Richard Henderson This is a multi-part message in MIME format. --------------080209080801060908090107 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Hi Bill, sending text only e-mails might help. Usually git send-email is better than using KMail or other mail software. Use tools like git gui to get a correct signature. Any optional personal comments should come directly after the line with ---. Could you please re-send your patch? Check it before sending with scripts/checkpatch.pl. Maybe this looks like much regulations to fix a bug, but some rules are necessary to keep a project like QEMU alive. Cc'ing Paolo and Richard because this might be an important bug fix for the next release. (scripts/get_maintainer.pl tells which maintainers should be cc'ed). Regards Stefan Am 09.03.2015 um 23:02 schrieb Bill Paul: > > Nobody has commented on this yet. According to my reading of the Intel > documentation, the SYSRET instruction is supposed to force the RPL > bits of the %ss register to 3 when returning to user mode. The actual > sequence is: > > SS.Selector <-- (IA32_STAR[63:48]+8) OR 3; (* RPL forced to 3 *) > > However, the code in helper_sysret() leaves them at 0 (in other words, > the "OR 3" part of the above sequence is missing). It does set the > privilege level bits of %cs correctly though. > > This has caused me trouble with some of my VxWorks development: code > that runs okay on real hardware will crash on QEMU, unless I apply the > patch below. > > Can someone confirm that this is in fact a real bug? The Intel > architecture manual seems quite clear about the SYSRET behavior. The > bug seems to have been around as far back as QEMU 0.10.5. > > I am using QEMU 2.2.0 on FreeBSD/amd64 9.1-RELEASE. > > -Bill > > Signed-off-by: Bill Paul > > --- > > target-i386/seg_helper.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c > > index fa374d0..2bc757a 100644 > > --- a/target-i386/seg_helper.c > > +++ b/target-i386/seg_helper.c > > @@ -1043,7 +1043,7 @@ void helper_sysret(CPUX86State *env, int dflag) > > DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); > > env->eip = (uint32_t)env->regs[R_ECX]; > > } > > - cpu_x86_load_seg_cache(env, R_SS, selector + 8, > > + cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3, > > 0, 0xffffffff, > > DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | > > DESC_S_MASK | (3 << DESC_DPL_SHIFT) | > > @@ -1056,7 +1056,7 @@ void helper_sysret(CPUX86State *env, int dflag) > > DESC_S_MASK | (3 << DESC_DPL_SHIFT) | > > DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); > > env->eip = (uint32_t)env->regs[R_ECX]; > > - cpu_x86_load_seg_cache(env, R_SS, selector + 8, > > + cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3, > > 0, 0xffffffff, > > DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | > > DESC_S_MASK | (3 << DESC_DPL_SHIFT) | > > -- > > 1.8.0 > > -- > > ============================================================================= > > -Bill Paul (510) 749-2329 | Senior Member of Technical Staff, > > wpaul@windriver.com | Master of Unix-Fu - Wind River Systems > > ============================================================================= > > "I put a dollar in a change machine. Nothing changed." - George Carlin > > ============================================================================= > --------------080209080801060908090107 Content-Type: text/html; charset=windows-1252 Content-Transfer-Encoding: 7bit
Hi Bill,

sending text only e-mails might help. Usually git send-email is better than using KMail or other mail software.
Use tools like git gui to get a correct signature. Any optional personal comments should come directly after
the line with ---. Could you please re-send your patch? Check it before sending with scripts/checkpatch.pl.

Maybe this looks like much regulations to fix a bug, but some rules are necessary to keep a project
like QEMU alive.

Cc'ing Paolo and Richard because this might be an important bug fix for the next release.
(scripts/get_maintainer.pl tells which maintainers should be cc'ed).

Regards
Stefan


Am 09.03.2015 um 23:02 schrieb Bill Paul:

Nobody has commented on this yet. According to my reading of the Intel documentation, the SYSRET instruction is supposed to force the RPL bits of the %ss register to 3 when returning to user mode. The actual sequence is:

SS.Selector <-- (IA32_STAR[63:48]+8) OR 3; (* RPL forced to 3 *)

However, the code in helper_sysret() leaves them at 0 (in other words, the "OR 3" part of the above sequence is missing). It does set the privilege level bits of %cs correctly though.

This has caused me trouble with some of my VxWorks development: code that runs okay on real hardware will crash on QEMU, unless I apply the patch below.

Can someone confirm that this is in fact a real bug? The Intel architecture manual seems quite clear about the SYSRET behavior. The bug seems to have been around as far back as QEMU 0.10.5.

I am using QEMU 2.2.0 on FreeBSD/amd64 9.1-RELEASE.

-Bill

Signed-off-by: Bill Paul <wpaul@windriver.com>

---

target-i386/seg_helper.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c

index fa374d0..2bc757a 100644

--- a/target-i386/seg_helper.c

+++ b/target-i386/seg_helper.c

@@ -1043,7 +1043,7 @@ void helper_sysret(CPUX86State *env, int dflag)

DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);

env->eip = (uint32_t)env->regs[R_ECX];

}

- cpu_x86_load_seg_cache(env, R_SS, selector + 8,

+ cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3,

0, 0xffffffff,

DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |

DESC_S_MASK | (3 << DESC_DPL_SHIFT) |

@@ -1056,7 +1056,7 @@ void helper_sysret(CPUX86State *env, int dflag)

DESC_S_MASK | (3 << DESC_DPL_SHIFT) |

DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);

env->eip = (uint32_t)env->regs[R_ECX];

- cpu_x86_load_seg_cache(env, R_SS, selector + 8,

+ cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3,

0, 0xffffffff,

DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |

DESC_S_MASK | (3 << DESC_DPL_SHIFT) |

--

1.8.0

--

=============================================================================

-Bill Paul (510) 749-2329 | Senior Member of Technical Staff,

wpaul@windriver.com | Master of Unix-Fu - Wind River Systems

=============================================================================

"I put a dollar in a change machine. Nothing changed." - George Carlin

=============================================================================


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