From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40845) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YVGUl-0003Xz-Dk for qemu-devel@nongnu.org; Tue, 10 Mar 2015 05:30:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YVGUh-0000Me-U9 for qemu-devel@nongnu.org; Tue, 10 Mar 2015 05:30:35 -0400 Received: from mail-db3on0075.outbound.protection.outlook.com ([157.55.234.75]:45504 helo=emea01-db3-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YVGUh-0000MT-Ib for qemu-devel@nongnu.org; Tue, 10 Mar 2015 05:30:31 -0400 Message-ID: <54FEB9A7.9030909@toganetworks.com> Date: Tue, 10 Mar 2015 11:30:15 +0200 From: Shlomo Pongratz MIME-Version: 1.0 References: <1425912119-15681-1-git-send-email-shlomo.pongratz@toganetworks.com> In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH RFC] Implement GIC-500 from GICv3 family for arm64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Shlomo Pongratz , Claudio Fontana , QEMU Developers On 09 =D8=A2=D8=B0=D8=A7=D8=B1, 2015 =D9=85 05:13, Peter Maydell wrote: > On 9 March 2015 at 23:41, wrote: >> From: Shlomo Pongratz >> >> This patch is a first step toward 128 cores support for arm64. >> >> At first only 64 cores are supported for two reasons: >> First the largest integer type has the size of 64 bits and modifying >> essential data structures in order to support 128 cores will require >> the usage of bitops. >> Second currently the Linux (kernel) can be configured to support >> up to 64 cores thus there is no urgency with 128 cores support. >> >> Things left to do: >> >> Currently the booting Linux may got stuck. The probability of getting st= uck >> increases with the number of cores. I'll appreciate core review. >> >> There is a need to support flexible clusters size. The GIC-500 can suppo= rt >> up to 128 cores, up to 32 clusters and up to 8 cores is a cluster. >> So for example, if one wishes to have 16 cores, the options are: >> 2 clusters of 8 cores each, 4 clusters with 4 cores each >> Currently only the first option is supported. >> There is an issue of passing clock affinity to via the dtb. In the dtb >> >> interrupt section there are only 24 bit left to affinity since the >> variable is a 32 bit entity and 8 bits are reserved for flags. >> See Documentation/devicetree/bindings/arm/arch_timer.txt. >> Note that this issue is not seems to be critical as when checking >> /proc/irq/3/smp_affinity with 32 cores all 32 bits are one. >> >> The last issue is to add support for 128 cores. This requires the usage >> of bitops and currently can be tested up to 64 cores. >> >> Signed-off-by: Shlomo Pongratz >> --- >> hw/arm/Makefile.objs | 2 +- >> hw/arm/virtv2.c | 774 +++++++++++++++++ >> hw/intc/Makefile.objs | 2 + >> hw/intc/arm_gic_common.c | 2 + >> hw/intc/arm_gicv3.c | 1596 ++++++++++++++++++++++++++++= ++++++++ >> hw/intc/arm_gicv3_common.c | 188 +++++ >> hw/intc/gicv3_internal.h | 153 ++++ >> include/hw/intc/arm_gicv3.h | 44 + >> include/hw/intc/arm_gicv3_common.h | 136 +++ >> target-arm/cpu.c | 1 + >> target-arm/cpu.h | 6 + >> target-arm/cpu64.c | 92 +++ >> target-arm/helper.c | 12 +- >> target-arm/psci.c | 18 +- >> target-arm/translate-a64.c | 14 + >> 15 files changed, 3034 insertions(+), 6 deletions(-) >> create mode 100644 hw/arm/virtv2.c >> create mode 100644 hw/intc/arm_gicv3.c >> create mode 100644 hw/intc/arm_gicv3_common.c >> create mode 100644 hw/intc/gicv3_internal.h >> create mode 100644 include/hw/intc/arm_gicv3.h >> create mode 100644 include/hw/intc/arm_gicv3_common.h > This is way too big to review as a single patch; you should > find a way to split it into a series of multiple coherent patches. > > thanks > -- PMM Hi Peter, Thanks I'll do that. Best regards, S.P. ---------------------------------------------------------------------------= ---------------------------------------------------------------------- This email and any files transmitted and/or attachments with it are confide= ntial and proprietary information of Toga Networks Ltd., and intended solely for the use of the individual or en= tity to whom they are addressed. If you have received this email in error please notify the system manager. = This message contains confidential information of Toga Networks Ltd., and is intended only for the individual = named. If you are not the named addressee you should not disseminate, distribute or copy this e-mail. Pleas= e notify the sender immediately by e-mail if you have received this e-mail by mistake and delete this e-mai= l from your system. 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