From mboxrd@z Thu Jan 1 00:00:00 1970 From: Archit Taneja Subject: Re: [PATCH 5/5] drm/msm/mdp5: Add hardware configuration for msm8x16 Date: Thu, 12 Mar 2015 14:34:42 +0530 Message-ID: <550156AA.6050005@codeaurora.org> References: <1425407775-7704-1-git-send-email-sviau@codeaurora.org> <1425906667-3363-1-git-send-email-sviau@codeaurora.org> <1425906667-3363-6-git-send-email-sviau@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1425906667-3363-6-git-send-email-sviau@codeaurora.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Stephane Viau , dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org SGksCgpPbiAwMy8wOS8yMDE1IDA2OjQxIFBNLCBTdGVwaGFuZSBWaWF1IHdyb3RlOgo+IFRoaXMg Y2hhbmdlIGFkZHMgdGhlIGh3IGNvbmZpZ3VyYXRpb24gZm9yIG1zbTh4MTYgY2hpcHNldHMgaW4K PiBtZHA1X2NmZyBtb2R1bGUuCj4KPiBOb3RlIHRoYXQgb25seSBvbmUgZXh0ZXJuYWwgZGlzcGxh eSBpbnRlcmZhY2UgaXMgcHJlc2VudCBpbiB0aGlzCj4gY29uZmlndXJhdGlvbiAoRFNJKSBidXQg aGFzIG5vdCBiZWVuIGVuYWJsZWQgeWV0LiBJdCB3aWxsIGJlIGVuYWJsZWQKPiBvbmNlIGRybS9t c20gZHJpdmVyIHN1cHBvcnRzIERTSSBjb25uZWN0b3JzLgo+Cj4gU2lnbmVkLW9mZi1ieTogU3Rl cGhhbmUgVmlhdSA8c3ZpYXVAY29kZWF1cm9yYS5vcmc+Cj4gLS0tCj4gICBkcml2ZXJzL2dwdS9k cm0vbXNtL21kcC9tZHA1L21kcDVfY2ZnLmMgfCA1MSArKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrKy0KPiAgIDEgZmlsZSBjaGFuZ2VkLCA1MCBpbnNlcnRpb25zKCspLCAxIGRlbGV0aW9u KC0pCj4KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2Nm Zy5jIGIvZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2NmZy5jCj4gaW5kZXggOTZl YTZkZC4uOWZmN2FjMSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vbXNtL21kcC9tZHA1 L21kcDVfY2ZnLmMKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL21kcC9tZHA1L21kcDVfY2Zn LmMKPiBAQCAtMSw1ICsxLDUgQEAKPiAgIC8qCj4gLSAqIENvcHlyaWdodCAoYykgMjAxNCBUaGUg TGludXggRm91bmRhdGlvbi4gQWxsIHJpZ2h0cyByZXNlcnZlZC4KPiArICogQ29weXJpZ2h0IChj KSAyMDE0LTIwMTUgVGhlIExpbnV4IEZvdW5kYXRpb24uIEFsbCByaWdodHMgcmVzZXJ2ZWQuCj4g ICAgKgo+ICAgICogVGhpcyBwcm9ncmFtIGlzIGZyZWUgc29mdHdhcmU7IHlvdSBjYW4gcmVkaXN0 cmlidXRlIGl0IGFuZC9vciBtb2RpZnkKPiAgICAqIGl0IHVuZGVyIHRoZSB0ZXJtcyBvZiB0aGUg R05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgdmVyc2lvbiAyIGFuZAo+IEBAIC0xNTAsMTAgKzE1 MCw1OSBAQCBjb25zdCBzdHJ1Y3QgbWRwNV9jZmdfaHcgYXBxODA4NF9jb25maWcgPSB7Cj4gICAJ Lm1heF9jbGsgPSAzMjAwMDAwMDAsCj4gICB9Owo+Cj4gK2NvbnN0IHN0cnVjdCBtZHA1X2NmZ19o dyBtc204eDE2X2NvbmZpZyA9IHsKPiArCS5uYW1lID0gIm1zbTh4MTYiLAo+ICsJLm1kcCA9IHsK PiArCQkuY291bnQgPSAxLAo+ICsJCS5iYXNlID0geyAweDAxMDAwIH0sCj4gKwl9LAo+ICsJLnNt cCA9IHsKPiArCQkubW1iX2NvdW50ID0gOCwKPiArCQkubW1iX3NpemUgPSA4MTkyLAo+ICsJCS5j bGllbnRzID0gewo+ICsJCQlbU1NQUF9WSUcwXSA9IDEsIFtTU1BQX0RNQTBdID0gNCwKPiArCQkJ W1NTUFBfUkdCMF0gPSA3LCBbU1NQUF9SR0IxXSA9IDgsCj4gKwkJfSwKPiArCX0sCj4gKwkuY3Rs ID0gewo+ICsJCS5jb3VudCA9IDUsCj4gKwkJLmJhc2UgPSB7IDB4MDIwMDAsIDB4MDIyMDAsIDB4 MDI0MDAsIDB4MDI2MDAsIDB4MDI4MDAgfSwKPiArCX0sCj4gKwkucGlwZV92aWcgPSB7Cj4gKwkJ LmNvdW50ID0gMSwKPiArCQkuYmFzZSA9IHsgMHgwNTAwMCB9LAo+ICsJfSwKPiArCS5waXBlX3Jn YiA9IHsKPiArCQkuY291bnQgPSAyLAo+ICsJCS5iYXNlID0geyAweDE1MDAwLCAweDE3MDAwIH0s Cj4gKwl9LAo+ICsJLnBpcGVfZG1hID0gewo+ICsJCS5jb3VudCA9IDEsCj4gKwkJLmJhc2UgPSB7 IDB4MjUwMDAgfSwKPiArCX0sCj4gKwkubG0gPSB7Cj4gKwkJLmNvdW50ID0gMiwgLyogTE0wIGFu ZCBMTTMgKi8KPiArCQkuYmFzZSA9IHsgMHg0NTAwMCwgMHg0ODAwMCB9LAo+ICsJCS5uYl9zdGFn ZXMgPSA1LAo+ICsJfSwKPiArCS5kc3BwID0gewo+ICsJCS5jb3VudCA9IDEsCj4gKwkJLmJhc2Ug PSB7IDB4NTUwMDAgfSwKPiArCj4gKwl9LAo+ICsJLmludGYgPSB7Cj4gKwkJLmNvdW50ID0gMSwg LyogSU5URl8xICovCj4gKwkJLmJhc2UgPSB7IDB4NkI4MDAgfSwKCldlIHdvdWxkIG5lZWQgdG8g cHV0IHRoZSBvdGhlciBub24tZXhpc3RlbnQgSU5URl8wLCBJTlRGXzIgYW5kIElOVEZfMyAKYmFz ZSBhZGRyZXNzZXMgaGVyZSB0b28sIHNvIHRoYXQgdGhlIHdyaXRlcyB0byAKUkVHX01EUDVfSU5U Rl9USU1JTkdfRU5HSU5FX0VOIGluIHRoZSBwYXRjaCAiTWFrZSB0aGUgaW50ZiBjb25uZWN0aW9u IGluIApjb25maWcgbW9kdWxlIiBhY2Nlc3MgdGhlIGNvcnJlY3QgcmVnaXN0ZXJzLgoKQXJjaGl0 Cgo+ICsJfSwKPiArCS8qIFRPRE8gZW5hYmxlIC5pbnRmc1tdIHdpdGggWzFdID0gSU5URl9EU0ks IG9uY2UgRFNJIGlzIGltcGxlbWVudGVkICovCj4gKwkubWF4X2NsayA9IDMyMDAwMDAwMCwKPiAr fTsKPiArCj4gICBzdGF0aWMgY29uc3Qgc3RydWN0IG1kcDVfY2ZnX2hhbmRsZXIgY2ZnX2hhbmRs ZXJzW10gPSB7Cj4gICAJeyAucmV2aXNpb24gPSAwLCAuY29uZmlnID0geyAuaHcgPSAmbXNtOHg3 NF9jb25maWcgfSB9LAo+ICAgCXsgLnJldmlzaW9uID0gMiwgLmNvbmZpZyA9IHsgLmh3ID0gJm1z bTh4NzRfY29uZmlnIH0gfSwKPiAgIAl7IC5yZXZpc2lvbiA9IDMsIC5jb25maWcgPSB7IC5odyA9 ICZhcHE4MDg0X2NvbmZpZyB9IH0sCj4gKwl7IC5yZXZpc2lvbiA9IDYsIC5jb25maWcgPSB7IC5o dyA9ICZtc204eDE2X2NvbmZpZyB9IH0sCj4gICB9Owo+Cj4KPgoKLS0gClF1YWxjb21tIElubm92 YXRpb24gQ2VudGVyLCBJbmMuIGlzIGEgbWVtYmVyIG9mIENvZGUgQXVyb3JhIEZvcnVtLAphIExp bnV4IEZvdW5kYXRpb24gQ29sbGFib3JhdGl2ZSBQcm9qZWN0Cl9fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRl dmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21h aWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753810AbbCLJFA (ORCPT ); Thu, 12 Mar 2015 05:05:00 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:53779 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752536AbbCLJEz (ORCPT ); Thu, 12 Mar 2015 05:04:55 -0400 Message-ID: <550156AA.6050005@codeaurora.org> Date: Thu, 12 Mar 2015 14:34:42 +0530 From: Archit Taneja User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: Stephane Viau , dri-devel@lists.freedesktop.org CC: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, robdclark@gmail.com Subject: Re: [PATCH 5/5] drm/msm/mdp5: Add hardware configuration for msm8x16 References: <1425407775-7704-1-git-send-email-sviau@codeaurora.org> <1425906667-3363-1-git-send-email-sviau@codeaurora.org> <1425906667-3363-6-git-send-email-sviau@codeaurora.org> In-Reply-To: <1425906667-3363-6-git-send-email-sviau@codeaurora.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 03/09/2015 06:41 PM, Stephane Viau wrote: > This change adds the hw configuration for msm8x16 chipsets in > mdp5_cfg module. > > Note that only one external display interface is present in this > configuration (DSI) but has not been enabled yet. It will be enabled > once drm/msm driver supports DSI connectors. > > Signed-off-by: Stephane Viau > --- > drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 51 ++++++++++++++++++++++++++++++++- > 1 file changed, 50 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c > index 96ea6dd..9ff7ac1 100644 > --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c > +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c > @@ -1,5 +1,5 @@ > /* > - * Copyright (c) 2014 The Linux Foundation. All rights reserved. > + * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved. > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License version 2 and > @@ -150,10 +150,59 @@ const struct mdp5_cfg_hw apq8084_config = { > .max_clk = 320000000, > }; > > +const struct mdp5_cfg_hw msm8x16_config = { > + .name = "msm8x16", > + .mdp = { > + .count = 1, > + .base = { 0x01000 }, > + }, > + .smp = { > + .mmb_count = 8, > + .mmb_size = 8192, > + .clients = { > + [SSPP_VIG0] = 1, [SSPP_DMA0] = 4, > + [SSPP_RGB0] = 7, [SSPP_RGB1] = 8, > + }, > + }, > + .ctl = { > + .count = 5, > + .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 }, > + }, > + .pipe_vig = { > + .count = 1, > + .base = { 0x05000 }, > + }, > + .pipe_rgb = { > + .count = 2, > + .base = { 0x15000, 0x17000 }, > + }, > + .pipe_dma = { > + .count = 1, > + .base = { 0x25000 }, > + }, > + .lm = { > + .count = 2, /* LM0 and LM3 */ > + .base = { 0x45000, 0x48000 }, > + .nb_stages = 5, > + }, > + .dspp = { > + .count = 1, > + .base = { 0x55000 }, > + > + }, > + .intf = { > + .count = 1, /* INTF_1 */ > + .base = { 0x6B800 }, We would need to put the other non-existent INTF_0, INTF_2 and INTF_3 base addresses here too, so that the writes to REG_MDP5_INTF_TIMING_ENGINE_EN in the patch "Make the intf connection in config module" access the correct registers. Archit > + }, > + /* TODO enable .intfs[] with [1] = INTF_DSI, once DSI is implemented */ > + .max_clk = 320000000, > +}; > + > static const struct mdp5_cfg_handler cfg_handlers[] = { > { .revision = 0, .config = { .hw = &msm8x74_config } }, > { .revision = 2, .config = { .hw = &msm8x74_config } }, > { .revision = 3, .config = { .hw = &apq8084_config } }, > + { .revision = 6, .config = { .hw = &msm8x16_config } }, > }; > > > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project