From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sylwester Nawrocki Subject: Re: [RFC PATCH 2/3] arm/exynos/pm_domains: add support for async-bridge clocks Date: Thu, 12 Mar 2015 14:05:39 +0100 Message-ID: <55018F23.3010402@samsung.com> References: <1423139739-19881-1-git-send-email-a.hajda@samsung.com> <1423139739-19881-3-git-send-email-a.hajda@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-reply-to: <1423139739-19881-3-git-send-email-a.hajda@samsung.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Andrzej Hajda , linux-samsung-soc@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Liquid.Acid@gmx.net, Kyungmin Park , Kukjin Kim , javier.martinez@collabora.co.uk, Marek Szyprowski List-Id: linux-samsung-soc@vger.kernel.org T24gMDUvMDIvMTUgMTM6MzUsIEFuZHJ6ZWogSGFqZGEgd3JvdGU6Cj4gU2luY2UgRXh5bm9zNTQy MCB0aGVyZSBhcmUgYXN5bmMtYnJpZGdlcyAoQVNCKSBiZXR3ZWVuIGRpZmZlcmVudCBJUHMuIFRo ZXNlCj4gYnJpZGdlcyBtdXN0IGJlIG9wZXJhdGlvbmFsIGR1cmluZyBwb3dlciBkb21haW4gb24v b2ZmLCBpZS4gY2xvY2tzIHVzZWQKPiBieSB0aGVzZSBicmlkZ2VzIHNob3VsZCBiZSBlbmFibGVk Lgo+IFRoaXMgcGF0Y2ggZW5hYmxlZCB0aGVzZSBjbG9ja3MgZHVyaW5nIGRvbWFpbiBvbi9vZmYu Cj4gCj4gU2lnbmVkLW9mZi1ieTogQW5kcnplaiBIYWpkYSA8YS5oYWpkYUBzYW1zdW5nLmNvbT4K ClJldmlld2VkLWJ5OiBTeWx3ZXN0ZXIgTmF3cm9ja2kgPHMubmF3cm9ja2lAc2Ftc3VuZy5jb20+ Cgo+IC0tLQo+ICBhcmNoL2FybS9tYWNoLWV4eW5vcy9wbV9kb21haW5zLmMgfCAyNyArKysrKysr KysrKysrKysrKysrKysrKy0tLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDIzIGluc2VydGlvbnMoKyks IDQgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtL21hY2gtZXh5bm9zL3Bt X2RvbWFpbnMuYyBiL2FyY2gvYXJtL21hY2gtZXh5bm9zL3BtX2RvbWFpbnMuYwo+IGluZGV4IDBl MmJjMzYuLmVjZmY1MjIgMTAwNjQ0Cj4gLS0tIGEvYXJjaC9hcm0vbWFjaC1leHlub3MvcG1fZG9t YWlucy5jCj4gKysrIGIvYXJjaC9hcm0vbWFjaC1leHlub3MvcG1fZG9tYWlucy5jCj4gQEAgLTM3 LDYgKzM3LDcgQEAgc3RydWN0IGV4eW5vc19wbV9kb21haW4gewo+ICAJc3RydWN0IGNsayAqb3Nj Y2xrOwo+ICAJc3RydWN0IGNsayAqY2xrW01BWF9DTEtfUEVSX0RPTUFJTl07Cj4gIAlzdHJ1Y3Qg Y2xrICpwY2xrW01BWF9DTEtfUEVSX0RPTUFJTl07Cj4gKwlzdHJ1Y3QgY2xrICphc2JfY2xrW01B WF9DTEtfUEVSX0RPTUFJTl07Cj4gIH07Cj4gIAo+ICBzdGF0aWMgaW50IGV4eW5vc19wZF9wb3dl cihzdHJ1Y3QgZ2VuZXJpY19wbV9kb21haW4gKmRvbWFpbiwgYm9vbCBwb3dlcl9vbikKPiBAQCAt NDUsMTQgKzQ2LDE5IEBAIHN0YXRpYyBpbnQgZXh5bm9zX3BkX3Bvd2VyKHN0cnVjdCBnZW5lcmlj X3BtX2RvbWFpbiAqZG9tYWluLCBib29sIHBvd2VyX29uKQo+ICAJdm9pZCBfX2lvbWVtICpiYXNl Owo+ICAJdTMyIHRpbWVvdXQsIHB3cjsKPiAgCWNoYXIgKm9wOwo+ICsJaW50IGk7Cj4gIAo+ICAJ cGQgPSBjb250YWluZXJfb2YoZG9tYWluLCBzdHJ1Y3QgZXh5bm9zX3BtX2RvbWFpbiwgcGQpOwo+ ICAJYmFzZSA9IHBkLT5iYXNlOwo+ICAKPiArCWZvciAoaSA9IDA7IGkgPCBNQVhfQ0xLX1BFUl9E T01BSU47IGkrKykgewo+ICsJCWlmIChJU19FUlIocGQtPmFzYl9jbGtbaV0pKQo+ICsJCQlicmVh azsKPiArCQljbGtfcHJlcGFyZV9lbmFibGUocGQtPmFzYl9jbGtbaV0pOwo+ICsJfQo+ICsKPiAg CS8qIFNldCBvc2NjbGsgYmVmb3JlIHBvd2VyaW5nIG9mZiBhIGRvbWFpbiovCj4gIAlpZiAoIXBv d2VyX29uKSB7Cj4gLQkJaW50IGk7Cj4gLQo+ICAJCWZvciAoaSA9IDA7IGkgPCBNQVhfQ0xLX1BF Ul9ET01BSU47IGkrKykgewo+ICAJCQlpZiAoSVNfRVJSKHBkLT5jbGtbaV0pKQo+ICAJCQkJYnJl YWs7Cj4gQEAgLTgxLDggKzg3LDYgQEAgc3RhdGljIGludCBleHlub3NfcGRfcG93ZXIoc3RydWN0 IGdlbmVyaWNfcG1fZG9tYWluICpkb21haW4sIGJvb2wgcG93ZXJfb24pCj4gIAo+ICAJLyogUmVz dG9yZSBjbG9ja3MgYWZ0ZXIgcG93ZXJpbmcgb24gYSBkb21haW4qLwo+ICAJaWYgKHBvd2VyX29u KSB7Cj4gLQkJaW50IGk7Cj4gLQo+ICAJCWZvciAoaSA9IDA7IGkgPCBNQVhfQ0xLX1BFUl9ET01B SU47IGkrKykgewo+ICAJCQlpZiAoSVNfRVJSKHBkLT5jbGtbaV0pKQo+ICAJCQkJYnJlYWs7Cj4g QEAgLTkyLDYgKzk2LDEyIEBAIHN0YXRpYyBpbnQgZXh5bm9zX3BkX3Bvd2VyKHN0cnVjdCBnZW5l cmljX3BtX2RvbWFpbiAqZG9tYWluLCBib29sIHBvd2VyX29uKQo+ICAJCX0KPiAgCX0KPiAgCj4g Kwlmb3IgKGkgPSAwOyBpIDwgTUFYX0NMS19QRVJfRE9NQUlOOyBpKyspIHsKPiArCQlpZiAoSVNf RVJSKHBkLT5hc2JfY2xrW2ldKSkKPiArCQkJYnJlYWs7Cj4gKwkJY2xrX2Rpc2FibGVfdW5wcmVw YXJlKHBkLT5hc2JfY2xrW2ldKTsKPiArCX0KPiArCj4gIAlyZXR1cm4gMDsKPiAgfQo+ICAKPiBA QCAtMTM3LDYgKzE0NywxNSBAQCBzdGF0aWMgX19pbml0IGludCBleHlub3M0X3BtX2luaXRfcG93 ZXJfZG9tYWluKHZvaWQpCj4gIAkJcGQtPnBkLnBvd2VyX29mZiA9IGV4eW5vc19wZF9wb3dlcl9v ZmY7Cj4gIAkJcGQtPnBkLnBvd2VyX29uID0gZXh5bm9zX3BkX3Bvd2VyX29uOwo+ICAKPiArCQlm b3IgKGkgPSAwOyBpIDwgTUFYX0NMS19QRVJfRE9NQUlOOyBpKyspIHsKPiArCQkJY2hhciBjbGtf bmFtZVs4XTsKPiArCj4gKwkJCXNucHJpbnRmKGNsa19uYW1lLCBzaXplb2YoY2xrX25hbWUpLCAi YXNiJWQiLCBpKTsKPiArCQkJcGQtPmFzYl9jbGtbaV0gPSBjbGtfZ2V0KGRldiwgY2xrX25hbWUp Owo+ICsJCQlpZiAoSVNfRVJSKHBkLT5hc2JfY2xrW2ldKSkKPiArCQkJCWJyZWFrOwo+ICsJCX0K PiArCj4gIAkJcGQtPm9zY2NsayA9IGNsa19nZXQoZGV2LCAib3NjY2xrIik7Cj4gIAkJaWYgKElT X0VSUihwZC0+b3NjY2xrKSkKPiAgCQkJZ290byBub19jbGs7Cj4gCgoKLS0gClN5bHdlc3RlciBO YXdyb2NraQpTYW1zdW5nIFImRCBJbnN0aXR1dGUgUG9sYW5kCl9fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRl dmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21h aWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932146AbbCLNGl (ORCPT ); Thu, 12 Mar 2015 09:06:41 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:22822 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754614AbbCLNGe (ORCPT ); Thu, 12 Mar 2015 09:06:34 -0400 X-AuditID: cbfec7f4-b7f126d000001e9a-98-55018ea63bf3 Message-id: <55018F23.3010402@samsung.com> Date: Thu, 12 Mar 2015 14:05:39 +0100 From: Sylwester Nawrocki User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.1.2 MIME-version: 1.0 To: Andrzej Hajda , linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Kyungmin Park , Kukjin Kim , javier.martinez@collabora.co.uk, Liquid.Acid@gmx.net, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: Re: [RFC PATCH 2/3] arm/exynos/pm_domains: add support for async-bridge clocks References: <1423139739-19881-1-git-send-email-a.hajda@samsung.com> <1423139739-19881-3-git-send-email-a.hajda@samsung.com> In-reply-to: <1423139739-19881-3-git-send-email-a.hajda@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHLMWRmVeSWpSXmKPExsVy+t/xq7rL+hhDDdYeEbS4te4cq8X8I0Di ytf3bBZHfxdY9D9+zWxxtukNu8XlXXPYLGac38dk0fXzJ5vF2iN32R24PP4+v87isXjTfjaP Tas62Tzudx9n8ujbsorR4/MmuQC2KC6blNSczLLUIn27BK6MBXeXsRT8EK3oWHaYpYFxumAX IyeHhICJxLvnb1kgbDGJC/fWs3UxcnEICSxllLjzbg4zhPOJUeLQqk9MIFW8AloSl89OYgax WQRUJZbvXcEIYrMJGEr0Hu0Ds0UFIiRO3t3DDlEvKPFj8j2wDSICXhKnZyxiAhnKLDCJSeLW rk6gQRwcwgKREnO680BMIYFaidY1LiDlnAIuEht/nWcECTML6Encv6gFEmYWkJfYvOYt8wRG gVlIFsxCqJqFpGoBI/MqRtHU0uSC4qT0XEO94sTc4tK8dL3k/NxNjJA4+LKDcfExq0OMAhyM Sjy8EX0MoUKsiWXFlbmHGCU4mJVEeEvbGUOFeFMSK6tSi/Lji0pzUosPMTJxcEo1MAqvV+T8 bb855uKyr6c0q29POnxQWl3VcqdT0O/j1WEXrI7d7DsYKBDzPjrsUcii+1sNvHuUpRnqPvK3 3GxpuTXn9ZprvVOnvJD3V1PivX660Wzl9MwJG84vTqhrPlkn/vtnmf4Ny89Bb1tc29185YWd w27y7KiVyjFUaLOw4W7cIPFnlbzLUyWW4oxEQy3mouJEALfhtClhAgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/02/15 13:35, Andrzej Hajda wrote: > Since Exynos5420 there are async-bridges (ASB) between different IPs. These > bridges must be operational during power domain on/off, ie. clocks used > by these bridges should be enabled. > This patch enabled these clocks during domain on/off. > > Signed-off-by: Andrzej Hajda Reviewed-by: Sylwester Nawrocki > --- > arch/arm/mach-exynos/pm_domains.c | 27 +++++++++++++++++++++++---- > 1 file changed, 23 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c > index 0e2bc36..ecff522 100644 > --- a/arch/arm/mach-exynos/pm_domains.c > +++ b/arch/arm/mach-exynos/pm_domains.c > @@ -37,6 +37,7 @@ struct exynos_pm_domain { > struct clk *oscclk; > struct clk *clk[MAX_CLK_PER_DOMAIN]; > struct clk *pclk[MAX_CLK_PER_DOMAIN]; > + struct clk *asb_clk[MAX_CLK_PER_DOMAIN]; > }; > > static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) > @@ -45,14 +46,19 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) > void __iomem *base; > u32 timeout, pwr; > char *op; > + int i; > > pd = container_of(domain, struct exynos_pm_domain, pd); > base = pd->base; > > + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { > + if (IS_ERR(pd->asb_clk[i])) > + break; > + clk_prepare_enable(pd->asb_clk[i]); > + } > + > /* Set oscclk before powering off a domain*/ > if (!power_on) { > - int i; > - > for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { > if (IS_ERR(pd->clk[i])) > break; > @@ -81,8 +87,6 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) > > /* Restore clocks after powering on a domain*/ > if (power_on) { > - int i; > - > for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { > if (IS_ERR(pd->clk[i])) > break; > @@ -92,6 +96,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) > } > } > > + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { > + if (IS_ERR(pd->asb_clk[i])) > + break; > + clk_disable_unprepare(pd->asb_clk[i]); > + } > + > return 0; > } > > @@ -137,6 +147,15 @@ static __init int exynos4_pm_init_power_domain(void) > pd->pd.power_off = exynos_pd_power_off; > pd->pd.power_on = exynos_pd_power_on; > > + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { > + char clk_name[8]; > + > + snprintf(clk_name, sizeof(clk_name), "asb%d", i); > + pd->asb_clk[i] = clk_get(dev, clk_name); > + if (IS_ERR(pd->asb_clk[i])) > + break; > + } > + > pd->oscclk = clk_get(dev, "oscclk"); > if (IS_ERR(pd->oscclk)) > goto no_clk; > -- Sylwester Nawrocki Samsung R&D Institute Poland