From mboxrd@z Thu Jan 1 00:00:00 1970 From: James Sullivan Subject: Re: [PATCH v3 0/2] kvm: x86: Implement handling of RH=1 for MSI delivery in KVM Date: Tue, 17 Mar 2015 09:33:26 -0600 Message-ID: <55084946.7090106@gmail.com> References: <1426555822-3280-1-git-send-email-sullivan.james.f@gmail.com> <5507E376.7020305@siemens.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: 7bit Cc: gleb@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com To: Jan Kiszka , kvm@vger.kernel.org Return-path: Received: from mail-pa0-f42.google.com ([209.85.220.42]:36280 "EHLO mail-pa0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753928AbbCQPfi (ORCPT ); Tue, 17 Mar 2015 11:35:38 -0400 Received: by padcy3 with SMTP id cy3so12873365pad.3 for ; Tue, 17 Mar 2015 08:35:38 -0700 (PDT) In-Reply-To: <5507E376.7020305@siemens.com> Sender: kvm-owner@vger.kernel.org List-ID: On 03/17/2015 02:19 AM, Jan Kiszka wrote: > > Once the kernel side is settled, would you mind looking into equivalent > support for QEMU's APIC as well? Just to keep it easy to switch between > both modes without too many functional restrictions. > > Thanks! > Jan > Good idea! I'm hoping to participate in GSoC working on shunting some interrupt handling devices out of the KVM and into QEMU, so that's definitely something I'll start to look into. -James