From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50193) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YYEkc-0002Gm-HY for qemu-devel@nongnu.org; Wed, 18 Mar 2015 10:15:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YYEkY-0006EW-6C for qemu-devel@nongnu.org; Wed, 18 Mar 2015 10:15:14 -0400 Message-ID: <5509882E.6080305@suse.de> Date: Wed, 18 Mar 2015 15:14:06 +0100 From: Alexander Graf MIME-Version: 1.0 References: <1426648281-13955-1-git-send-email-aik@ozlabs.ru> <55097F7A.7090809@suse.de> In-Reply-To: <55097F7A.7090809@suse.de> Content-Type: text/plain; charset=iso-8859-15; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH qemu] target-ppc: Remove never existed POWER5+ v0.0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-15?Q?Andreas_F=E4rber?= , Alexey Kardashevskiy , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org On 03/18/2015 02:36 PM, Andreas F=E4rber wrote: > s/existed/existing/ or "that never existed" > > Am 18.03.2015 um 04:11 schrieb Alexey Kardashevskiy: >> IBM uses low 16bits to specify a chip version of a POWER CPU. > "specify the chip version of a" > >> So there has never been an actual silicon with PVR =3D 0x003B0000. >> The first silicon would have PVR 0x003B0100 but it is very unlikely >> to find it in any machine shipped to any customer as it is was too raw= . > "as it was" > >> This removes CPU_POWERPC_POWER5P_v00 definition and changes > Maybe worth pointing out that the POWER5+_v0.0 QOM type was introduced > in recent commit d7586dc426472b5ad0f5c01b5c7c551eeb5a6003 (target-ppc: > Add versions to server CPU descriptions)? > >> POWER5+ and POWERgs aliases (which are synonyms) to point to >> POWER5+_v2.1 which can still be found in real machines. > FTR, 171777a4b38a0f6331ae60c2546a5baf84c4b359 (target-ppc: Turn POWER5g= s > CPU into alias for POWER5+) set the POWER5+ alias up as conflict > resolution before I enabled the #ifdef TODO'ed POWER5P code in > 35ebcb2b7a469739e6452d27379181bfbfc0388d (target-ppc: Prepare POWER5P > CPU family). > >> Signed-off-by: Alexey Kardashevskiy >> --- >> >> >> I asked Paul. He suggested that there has never been an actual >> POWER5 silicon with PVR which low 16 bits are zeroes, >> the first one would be 0x003B0100 but it would be so buggy so >> it would not be shipped to any real customer. >> And then he suggested to look at the real POWER5+ machine, >> we looked around and found one: >> >> cpu : POWER5+ (gs) >> clock : 1898.100000MHz >> revision : 2.0 (pvr 003b 0200) >> >> I believe 3b 0201 is also something real and it is defined already in = QEMU >> so here is a patch. > Yes, I have a 2.1, so having POWER5+ point to it should be fine, it > being the latest and now only one we have. > > Reviewed-by: Andreas F=E4rber > > Alex, can you tweak the commit message and apply this for 2.3 please, a= s > fixup for the too hastily applied fix? Sure. Thanks, applied to ppc-next. Alex